CN8237EBGB Mindspeed Technologies, CN8237EBGB Datasheet - Page 319

• Manufacturer Part Number: CN8237EBGB
• Description: ATM SAR 622Mbps 3.3V ABR/CBR/GFR/UBR/VBR 456-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8237EBGB

• Package: 456BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 622 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3.135 V

CN8237
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
14.6.1 Host Interrupt Status Registers
0x380—Host Processor Interrupt Status Register 0 (HOST_ISTAT0)
28237-DSH-001-C
NOTE(S):
1. L = Level-sensitive status—A logic 1 on the status bit causes an interrupt when enabled by the corresponding IMASK bit.
2. E = Event driven status—A 0 > 1 transition on the status bit causes an interrupt when enabled. Reading the status register
3. D = Dual Event status—A 0 > 1 and 1 > 0 transition on the status bit can be enabled to cause an interrupt. Reading the status
4. Only host reads reset the status bits in the HOST_ISTAT0 register.
29–24
21–19
15–12
9–4
Bit
31
30
23
22
18
17
16
11
10
3
2
1
0
Reading the status does not clear the status or interrupt. The source of the condition causing the status must be cleared
before the status or interrupt is cleared.
clears the status bit and the interrupt.
register clears the status bit and the interrupt.
Field
Size
1
1
6
1
1
3
1
1
1
4
1
1
6
1
1
1
1
Type
—
—
—
—
—
L
L
L
E
L
L
L
L
E
E
E
E
(1)
These two registers contain all interruptible status bits for the host processor. The
corresponding interrupt enables are located in the HOST_IMASKx registers.
GPI
PHY_INTR
Reserved
Reserved
HSTAT1
Reserved
GFC_LINK
RSM_RUN
RSM_HS_WRITE
Reserved
SEG_RUN
SEG_HS_WRITE
Reserved
AAL5_DSC_RLOVR
CELL_DSC_RLOVR
CELL_RCVD_RLOVR
CELL_XMT_RLOVR
Mindspeed Technologies
Name
This bit reflects the state of the GPI input pin.
PHY_INTR can be connected to a PHY interrupt source.
Read as 0.
Read as 0. Reserved for future status page expansion.
This bit is set when any bit in HOST_ISTAT1 is set.
Read as 0.
Set when three consecutive received cells have GFC
SET_A, SET_B, or HALT bits set.
Set when the reassembly machine is running. Will be
high when the RSM Coprocessor is processing a cell.
Indicates reassembly host status has been written by
CN8237 to status queues 0–15. For queue number, read
HOST_ST_WR which must be read in order to clear
status bit.
Read as 0.
Set when the segmentation machine is running. Will be
high when SEG_ENABLE bit in SEG_CTRL is high or
when processing the last cell after SEG_ENABLE is low.
Indicates segmentation host status has been written by
the CN8237 to status queues 0–15. For queue number,
read HOST_ST_WR which must be read in order to clear
status bit.
Read as 0.
Set on the occurrence of an AAL5_DSC_CNT rollover.
Set on the occurrence of a CELL_DSC_CNT rollover.
Set on the occurrence of a CELL_RCVD_CNT rollover.
Set on the occurrence of a CELL_XMIT_CNT rollover.
™
14.6 Counters and Status Registers
Description
14.0 CN8237 Registers
14-29