SC28L194A1BE NXP Semiconductors, SC28L194A1BE Datasheet - Page 6

• Manufacturer Part Number: SC28L194A1BE
• Description: UART Interface IC UART QUAD W/FIFO
• Manufacturer: NXP Semiconductors
• Type: Quad UARTr

Specifications of SC28L194A1BE

• Number Of Channels: 4
• Data Rate: 460.8 Kbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 3 V
• Supply Current: 30 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Package / Case: LQFP-80
• Description/function: Quad UART
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V, 5 V
• Lead Free Status / Rohs Status: Details
• Other names: SC28L194A1BE,557

Philips Semiconductors
may be left unused if the internal BRG is not used and the X1 signal
is not selected for any counter input.
Sclk - System Clock
A clock frequency, within the limits specified in the electrical
specifications, must be supplied for the system clock Sclk. To
ensure the proper operation of internal controllers, the Sclk
frequency provided, must be strictly greater than twice the frequency
of X1 crystal clock, or any external 1x data clock input. The system
clock serves as the basic timing reference for the host interface and
other internal circuits.
Baud Rate Generator BRG
The baud rate generator operates from the oscillator or external
X1/CCLK clock input and is capable of generating 22 commonly
used data communications baud rates ranging from 50 to 230.4K
baud. These common rates may be doubled (up to 460.8 and 500K
baud) when faster clocks are used on the X1/X2 clock inputs. (See
Receiver and Transmitter Clock Select Register descriptions.) All of
these are available simultaneously for use by any receiver or
transmitter. The clock outputs from the BRG are at 16X the actual
baud rate.
BRG Counters (Used for random baud rate generation)
The two BRG Timers are programmable 16 bit dividers that are used
for generating miscellaneous clocks. These clocks may be used by
any or all of the receivers and transmitters in the Octart or output on
the general purpose output pin GPO.
Each timer unit has eight different clock sources available to it as
described in the BRG Timer Control Register. (BRGTCR). Note that
the timer run and stop controls are also contained in this register.
The BRG Timers generate a symmetrical square wave whose half
period is equal in time to the division of the selected BRG Timer
clock source by the number loaded to the BRG Timer Reload
Registers ( BRGTRU and BRGTRL). Thus, the output frequency will
be the clock source frequency divided by twice the value loaded to
the BRGTRU and BRGTRL registers. This is the result of counting
down once for the high portion of the output wave and once for the
low portion.
Whenever the these timers are selected via the receiver or
transmitter Clock Select register their output will be configured as a
16x clock for the respective receiver or transmitter. Therefore one
needs to program the timers to generate a clock 16 times faster than
the data rate. The formula for calculating ’n’, the number loaded to
the BRGTRU and BRGTRL registers, is shown below.
Note: ’n’ may assume values of 0 and 1. In previous Philips data
communications controllers these values were not allowed.
The BRG timer input frequency is controlled by the BRG Timer
control register (BRGTCR)
The frequency generated from the above formula will be at a rate 16
times faster than the desired baud rate. The transmitter and receiver
state machines include divide by 16 circuits which provide the final
frequency and provide various timing edges used in the qualifying
the serial data bit stream. Often this division will result in a
non-integer value; 26.3 for example. One may only program integer
numbers to a digital divider. There for 26 would be chosen. If 26.7
2006 Aug 15
Quad UART for 3.3 V and 5 V supply voltage
n
BRG Timer Input frequency
2 16 desired baud rate
– 1
6
was the result of the division then 27 would be chosen. This gives a
baud rate error of 0.3/26.3 or 0.3/26.7. which yields a percentage
error of 1.14% or 1.12% respectively; well within the ability of the
asynchronous mode of operation.
One should be cautious about the assumed benign effects of small
errors since the other receiver or transmitter with which one is
communicating may also have a small error in the precise baud rate.
In a “clean” communications environment using one start bit, eight
data bits and one stop bit the total difference allowed between the
transmitter and receiver frequency is approximately 4.6%. Less than
eight data bits will increase this percentage.
Channel Blocks
There are four channel blocks, each containing an I/O port control, a
data format control, and a single full duplex UART channel
consisting of a receiver and a transmitter with their associated 16
byte FIFOs. Each block has its own status register, interrupt status
and interrupt mask registers and their interface to the interrupt
arbitration system.
A highly programmable character recognition system is also
included in each block. This system is used for the Xon/Xoff flow
control and the multi-drop (”9 bit mode”) address character
recognition. It may also be used for general purpose character
recognition.
Four I/O pins are provided for each channel. These pins are
configured individually to be inputs or outputs. As inputs they may
be used to bring external data to the bus, as clocks for internal
functions or external control signals. Each I/O pin has a “Change of
State” detector. The change detectors are used to signal a change in
the signal level at the pin (Either 0 to 1 or 1 to 0) The level change
on these pins must be stable for 25 to 50 Us (two edges of the 38.4
KHz baud rate clock) before the detectors will signal a valid change.
These are typically used for interface signals from modems to the
QUART and from there to the host. See the description of the
“UART channel” under detailed descriptions below.
Character Recognition
Character recognition is specific to each of the four UARTs. Three
programmable characters are provided for the character recognition
for each channel. The three are general purpose in nature and may
be set to only cause an interrupt or to initiate some rather complex
operations specific to “Multi-drop” address recognition or in-band
Xon/Xoff flow control.
Character recognition is accomplished via CAM memory. The
Content Addressable Memory continually examines the incoming
data stream. Upon the recognition of a control character appropriate
bits are set in the Xon/Xoff Interrupt Status Register (XISR) and
Interrupt Status Register (ISR). The setting of these bit(s) will initiate
any of the automatic sequences or and/or an interrupt that may have
enabled via the MR0 register.
The characters of the recognition system are not controlled by the
software or hardware reset. They do not have a pre-defined “reset
value”. They may, however, be loaded by a “Gang White” or “Gang
Load” command as described in the “Xon Xoff Characters”
paragraph.
Note: Character recognition is further described in the Minor Modes
of Operation.
SC28L194
Product data sheet