SC28L194A1BE NXP Semiconductors, SC28L194A1BE Datasheet - Page 41

• Manufacturer Part Number: SC28L194A1BE
• Description: UART Interface IC UART QUAD W/FIFO
• Manufacturer: NXP Semiconductors
• Type: Quad UARTr

Specifications of SC28L194A1BE

• Number Of Channels: 4
• Data Rate: 460.8 Kbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 3 V
• Supply Current: 30 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Package / Case: LQFP-80
• Description/function: Quad UART
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V, 5 V
• Lead Free Status / Rohs Status: Details
• Other names: SC28L194A1BE,557

Philips Semiconductors
AC ELECTRICAL SPECIFICATIONS FOR COMMERCIAL AND INDUSTRIAL (5V)
V
2006 Aug 15
Reset Timing
Bus Timing
I/O Port Pin Timing
Interrupt Timing
Tx/Rx Clock Timing
Transmitter Timing
Receiver Timing
CC
SYMBOL
SYMBOL
Quad UART for 3.3 V and 5 V supply voltage
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
F
F
t
F
F
t
t
t
t
ts
RES
AS
AH
t
t
C
CH
STP
RWS
RWH
DD
DF
DS
DH
RWD
PS
PH
PD
PD
IR
IR
DD
RX
TX
TXD
TCS
RXS
RXH
CS
CS
RX
TX
STRT
= 5.0V
4
4
4
4
1
10%, –40 to +85 C
FIG #
FIG. #
RESET pulse width
A0–A7 setup time before Sclk C3 rising edge
A0–A7 hold time after Sclk C3 rising edge
CEN setup time before Sclk C1 high (Sync)
CEN setup time before Sclk C2 high (Async)
CEN hold time after Sclk C3 high (Sync)
CEN hold time after Sclk C4 high (Async)
CEN high before next C2 to stop next cycle (Sync Mode)
W–Rn setup time before Sclk C2 rising edge
W–Rn hold time after Sclk C3 rising edge
Read cycle Data valid after Sclk C3 falling edge
Read cycle data bus floating after CEN high (Sync)
Read cycle data bus floating after C4 end high (Async)
Write cycle data setup time before Sclk C4 rising edge
Write cycle data hold time after Sclk C4 rising edge
High time between CEN low (Async)
I/O input setup time before Sclk C3 falling edge
I/O input hold time after Sclk C4 rising edge
I/O output valid from:
IRQN from:
IACKN cycle Data valid after Sclk C3 rising edge
RxC high or low time
RxC frequency
RxC frequency
TxC high or low time
TxC frequency
TxC frequency
TxD output delay from TxC low
TxC output delay from TxD output data
RxD data setup time to RxC high (data)
RxD data hold time from RxC high (data)
RxD data low time for receiving a valid Start Bit
Write Sclk C4 rising edge (write to IOPIOR)
Internal interrupt source active bid
Reset to IRQN inactive
Write IMR (set or clear IMR bit)
(16 X)
(1 X)
(16 X)
(1 X)
PARAMETER
PARAMETER
3
41
2
17/32
MIN.
–15
10
10
18
14
25
18
14
25
15
12
18
12
22
15
15
20
20
5
5
5
0
0
0
0
1
1
1
LIMITS
1
1
1
1
/
TYP.
/
/
/
2
2
2
2
12
10
10
14
32
26
12
32
–4
Sclk
2
8
3
3
8
4
1
8
7
4
6
Sclk
Sclk
Sclk
SC28L194
MAX.
Product data sheet
25
16
15
50
43
75
45
25
16
16
60
15
1
1
bit time
UNIT
UNIT
MHz
MHz
MHz
MHz
Sclk
Sclk
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns