SC28L92A1B NXP Semiconductors, SC28L92A1B Datasheet - Page 13

• Manufacturer Part Number: SC28L92A1B
• Description: UART Interface IC UART DUAL W/FIFO
• Manufacturer: NXP Semiconductors
• Type: Dual UARTr

Specifications of SC28L92A1B

• Number Of Channels: 2
• Data Rate: 230.4 Kbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 3.3 V
• Supply Current: 25 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Package / Case: PQFP-44
• Description/function: Single-chip CMOS-LSI communications device
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V, 5 V
• Lead Free Status / Rohs Status: Details
• Other names: SC28L92A1B,557

NXP Semiconductors
Table 3.
[1]
6. Functional description
SC28L92_7
Product data sheet
Symbol
IP3
IP4
IP5
V
GND
n.c.
CC
HVQFN48 package die supply ground is connected to both GND pin and exposed center pad. GND pin must be connected to supply
ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be
soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region.
Pin
PLCC44 QFP44 HVQFN48
3
43
42
44
22
1, 23, 34 23
Pin description for 68xxx bus interface (Motorola)
6.1.1 Data bus buffer
6.1.2 Operation control
6.1.3 Interrupt control
6.1 Block diagram
41
37
36
38, 39
16, 17
The SC28L92 DUART consists of the following eight major sections: data bus buffer,
operation control, interrupt control, timing, communications channels A and B, input port
and output port. Refer to
The data bus buffer provides the interface between the external and internal data buses. It
is controlled by the operation control block to allow read and write operations to take place
between the controlling CPU and the DUART.
The operation control logic receives operation commands from the CPU and generates
appropriate signals to internal sections to control device operation. It contains address
decoding and read and write circuits to permit communications with the microprocessor
via the data bus.
A single active LOW interrupt output (INTRN) is provided which is activated upon the
occurrence of any of eight internal events. Associated with the interrupt system are the
Interrupt Mask Register (IMR) and the Interrupt Status Register (ISR). The IMR can be
programmed to select only certain conditions to cause INTRN to be asserted. The ISR
can be read by the CPU to determine all currently active interrupting conditions. Outputs
OP3 to OP7 can be programmed to provide discrete interrupt outputs for the transmitter,
45
41
40
42
18
6, 13, 24,
25, 36, 37,
43
[1]
Type
I
I
I
Pwr
Pwr
-
Rev. 07 — 19 December 2007
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
Section 4 “Block
Description
Input 3: General purpose input or channel A transmitter external clock
input (TxCA). When the external clock is used by the transmitter, the
transmitted data is clocked on the falling edge of the clock.
Input 4: General purpose input or channel A receiver external clock
input (RxCA). When the external clock is used by the receiver, the
received data is sampled on the rising edge of the clock.
Input 5: General purpose input or channel B transmitter external clock
input (TxCB). When the external clock is used by the transmitter, the
transmitted data is clocked on the falling edge of the clock.
Power Supply: 3.3 V
Ground
Not connected
…continued
diagram”.
10 % or 5 V
10 % supply input.
SC28L92
© NXP B.V. 2007. All rights reserved.
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