LH28F800SGHE-L70 Sharp Electronics, LH28F800SGHE-L70 Datasheet - Page 17

• Manufacturer Part Number: LH28F800SGHE-L70
• Manufacturer: Sharp Electronics

Specifications of LH28F800SGHE-L70

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 19b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP-I
• Program/erase Volt (typ): 2.7/3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Word Size: 16b
• Number Of Words: 512K
• Supply Current: 65mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

SR.7 = WRITE STATE MACHINE STATUS (WSMS)
SR.6 = ERASE SUSPEND STATUS (ESS)
SR.5 = ERASE AND CLEAR LOCK-BITS STATUS (ECLBS)
SR.4 = WORD WRITE AND SET LOCK-BIT STATUS (WWSLBS)
SR.3 = V
SR.2 = WORD WRITE SUSPEND STATUS (WWSS)
SR.1 = DEVICE PROTECT STATUS (DPS)
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
WSMS
1 = Ready
0 = Busy
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
1 = Error in Block Erase or Clear Lock-Bits
0 = Successful Block Erase or Clear Lock-Bits
1 = Error in Word Write or Set Permanent/Block Lock-Bit
0 = Successful Word Write or Set Permanent/Block Lock-Bit
1 = V
0 = V
1 = Word Write Suspended
0 = Word Write in Progress/Completed
1 = Permanent Lock-Bit, Block Lock-Bit and/or
0 = Unlock
7
WP#/RP# Lock Detected, Operation Abort
PP
PP
PP
STATUS (VPPS)
Low Detect, Operation Abort
OK
ESS
6
ECLBS
5
Table 6 Status Register Definition
WWSLBS
4
- 17 -
NOTES :
Check RY/BY# or SR.7 to determine block erase, word
write, or lock-bit configuration completion.
SR.6-0 are invalid while SR.7 =
If both SR.5 and SR.4 are
configuration attempt, an improper command sequence was
entered.
SR.3 does not provide a continuous indication of V
The WSM interrogates and indicates the V
Block Erase, Word Write, Set Block/Permanent Lock-Bit, or
Clear Block Lock-Bits command sequences. SR.3 is not
guaranteed to reports accurate feedback only when V
V
SR.1 does not provide a continuous indication of Permanent
and block lock-bit values. The WSM interrogates the
Permanent lock-bit, block lock-bit, WP# and RP# only after
Block Erase, Word Write, or Lock-Bit configuration command
sequences. It informs the system, depending on the attempted
operation, if the block lock-bit is set, permanent lock-bit is set,
and/or WP# is not V
lock and permanent lock configuration codes after writing the
Read Identifier Codes command indicates permanent and
block lock-bit status.
SR.0 is reserved for future use and should be masked out
when polling the status register.
PPH1/2/3
VPPS
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
3
.
WWSS
IH
2
, RP# is not V
"
1
"
s after a block erase or lock-bit
"
0
"
.
DPS
1
HH
. Reading the block
PP
level only after
PP
R
0
level.
PP
≠