LH28F800SGHE-L70 Sharp Electronics, LH28F800SGHE-L70 Datasheet - Page 11

• Manufacturer Part Number: LH28F800SGHE-L70
• Manufacturer: Sharp Electronics

Specifications of LH28F800SGHE-L70

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 19b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP-I
• Program/erase Volt (typ): 2.7/3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Word Size: 16b
• Number Of Words: 512K
• Supply Current: 65mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

NOTES :
1. Bus operations are defined in Table 2.
2. X = Any valid address within the device.
3. SRD = Data read from status register. See Table 6 for a
4. Following the Read Identifier Codes command, read
5. If the block is locked and the permanent lock-bit is not
Read Array/Reset
Read Identifier Codes
Read Status Register
Clear Status Register
Block Erase
Word Write
Block Erase and
Word Write Suspend
Block Erase and
Word Write Resume
Set Block Lock-Bit
Set Permanent Lock-Bit
Clear Block Lock-Bits
IA = Identifier code address : see Fig. 2.
BA = Address within the block being erased or locked.
WA = Address of memory location to be written.
WD = Data to be written at location WA. Data is latched
ID = Data read from identifier codes.
operations access manufacture, device, block lock, and
permanent lock codes. See Section 4.2 for read
identifier code data.
set, WP# must be at V
enable block erase or word write operations. Attempts to
issue a block erase or word write to a locked block while
WP# is V
COMMAND
on the rising edge of WE# or CE# (whichever
goes high first).
description of the status register bits.
IH
or RP# is V
HH
IH
.
or RP# must be at V
BUS CYCLES
REQ
≥ 2
1
2
2
1
1
2
2
2
1
2
Table 3 Command Definitions
’
D.
NOTE
5, 6
4
5
5
5
7
7
8
HH
Oper
to
- 11 -
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
(NOTE 1)
FIRST BUS CYCLE
6. Either 40H or 10H is recognized by the WSM as the
7. If the permanent lock-bit is set, WP# must be at V
8. If the permanent lock-bit is set, clear block lock-bits
9. Commands other than those shown above are reserved
Addr
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
word write setup.
RP# must be at V
be at V
lock-bit is set, a block lock-bit cannot be set. Once the
permanent lock-bit is set, permanent lock-bit reset is
unable.
operation is unable. The clear block lock-bits operation
simultaneously clears all block lock-bits. If the permanent
lock-bit is not set, the Clear Block Lock-Bits command
can be done while WP# is V
by SHARP for future device implementations and should
not be used.
WA
BA
BA
(NOTE 2)
X
X
X
X
X
X
X
X
(NOTE 9)
HH
Data
40H or 10H
to set the permanent lock-bit. If the permanent
D0H
FFH
90H
20H
B0H
60H
70H
50H
60H
60H
(NOTE 3)
HH
Oper
to set a block lock-bit. RP# must
Read
Read
Write
Write
Write
Write
Write
SECOND BUS CYCLE
(NOTE 1)
IH
or RP# is V
Addr
WA
BA
BA
IA
(NOTE 2)
X
X
X
HH
.
Data
SRD
D0H
D0H
F1H
01H
WD
ID
(NOTE 3)
IH
or