AM29DL323GT90WMI AMD (ADVANCED MICRO DEVICES), AM29DL323GT90WMI Datasheet

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AM29DL323GT90WMI

Manufacturer Part Number
AM29DL323GT90WMI
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet

Specifications of AM29DL323GT90WMI

Lead Free Status / Rohs Status
Not Compliant
S29PL127J/S29PL129J/S29PL064J/S29PL032J
128/128/64/32 Megabit (8/8/4/2 M x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Read/Write
Flash Memory with Enhanced VersatileIO
Distinctive Characteristics
ARCHITECTURAL ADVANTAGES
128/128/64/32 Mbit Page Mode devices
— Page size of 8 words: Fast page read access from
Single power supply operation
— Full Voltage range: 2.7 to 3.6 volt read, erase, and
Dual Chip Enable inputs (only in PL129J)
— Two CE# inputs control selection of each half of the
Simultaneous Read/Write Operation
— Data can be continuously read from one bank while
— Zero latency switching from write to read operations
FlexBank Architecture (PL127J/PL064J/PL032J)
— 4 separate banks, with up to two simultaneous
— Bank A:
— Bank B:
— Bank C:
— Bank D:
FlexBank Architecture (PL129J)
— 4 separate banks, with up to two simultaneous
— CE#1 controlled banks:
— CE#2 controlled banks:
random locations within the page
program operations for battery-powered applications
memory space
executing erase/program functions in another bank
operations per device
PL127J -16 Mbit (4 Kw x 8 and 32 Kw x 31)
PL064J - 8 Mbit (4 Kw x 8 and 32 Kw x 15)
PL032J - 4 Mbit (4 Kw x 8 and 32 Kw x 7)
PL127J - 48 Mbit (32 Kw x 96)
PL064J - 24 Mbit (32 Kw x 48)
PL032J - 12 Mbit (32 Kw x 24)
PL127J - 48 Mbit (32 Kw x 96)
PL064J - 24 Mbit (32 Kw x 48)
PL032J - 12 Mbit (32 Kw x 24)
PL127J -16 Mbit (4 Kw x 8 and 32 Kw x 31)
PL064J - 8 Mbit (4 Kw x 8 and 32 Kw x 15)
PL032J - 4 Mbit (4 Kw x 8 and 32 Kw x 7)
operations per device
Bank 1A:
PL129J - 16Mbit (4Kw x 8 and 32Kw x 31)
Bank 1B:
PL129J - 48Mbit (32Kw x 96)
Bank 2A:
PL129J - 48 Mbit (32Kw x 96)
Bank 2B:
PL129J - 16Mbit (4Kw x 8 and 32Kw x 31)
Publication Number 31107
Revision A
Amendment 5
PERFORMANCE CHARACTERISTICS
SOFTWARE FEATURES
TM
Enhanced VersatileI/O
— Output voltage generated and input voltages
— V
— 3V V
SecSi
— Up to 128 words accessible through a command
— Up to 64 factory-locked words
— Up to 64 customer-lockable words
Both top and bottom boot blocks in one device
Manufactured on 110 nm process technology
Data Retention: 20 years typical
Cycling Endurance: 1 million cycles per sector
typical
High Performance
— Page access times as fast as 20 ns
— Random access times as fast as 55 ns
Power consumption (typical values at 10 MHz)
— 45 mA active read current
— 17 mA program/erase current
— 0.2 µA typical standby mode current
Software command-set compatible with JEDEC
42.4 standard
— Backward compatible with Am29F, Am29LV,
CFI (Common Flash Interface) compliant
— Provides device-specific information to the system,
Erase Suspend / Erase Resume
— Suspends an erase operation to allow read or
Unlock Bypass Program command
— Reduces overall programming time when issuing
tolerated on all control inputs and I/Os is determined
by the voltage on the V
PL129J devices
sequence
Am29DL, and AM29PDL families and MBM29QM/RM,
MBM29LV, MBM29DL, MBM29PDL families
allowing host software to easily reconfigure for
different Flash devices
program operations in other sectors of same bank
multiple program command sequences
Control
IO
TM
options at 1.8 V and 3 V I/O for PL127J and
IO
(Secured Silicon) Sector region
Issue Date March 15, 2004
for PL064J and PL032J devices
TM
IO
(V
pin
IO
) Control
PRELIMINARY

Related parts for AM29DL323GT90WMI

AM29DL323GT90WMI Summary of contents

Page 1

... S29PL127J/S29PL129J/S29PL064J/S29PL032J 128/128/64/32 Megabit (8/8/4 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Distinctive Characteristics ARCHITECTURAL ADVANTAGES 128/128/64/32 Mbit Page Mode devices — Page size of 8 words: Fast page read access from random locations within the page Single power supply operation — ...

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HARDWARE FEATURES Ready/Busy# pin (RY/BY#) — Provides a hardware method of detecting program or erase cycle completion Hardware reset pin (RESET#) — Hardware method to reset the device to reading array data WP#/ ACC (Write Protect/Acceleration) input — ...

Page 3

... General Description The PL127J/PL129J/PL064J/PL032J is a 128/128/64/32 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device organized as 8/8/4/2 Mwords. The devices are offered in the following packages: 11mm x 8mm, 64-ball Fine-pitch BGA standalone (all) 9mm x 8mm, 80-ball Fine-pitch BGA standalone (PL127J and PL129J) ...

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... The device is entirely command set compatible with the JEDEC 42.4 sin- gle-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that controls the erase and programming cir- cuitry ...

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... Hardware Data Protection ............................................................................. 58 Low VCC Write Inhibit ................................................................................ 58 Write Pulse “Glitch” Protection ............................................................... 58 Logical Inhibit ................................................................................................... 58 Power-Up Write Inhibit ...............................................................................58 Common Flash Memory Interface (CFI Table 17. CFI Query Identification String .............................. 59 Table 18. System Interface String ........................................ 60 Table 19. Device Geometry Definition ................................... 60 Table 20. Primary Vendor-Specific Extended Query ................ 61 Command Definitions . . . . . . . . . . . . . . . . . . . . . . 63 Reading Array Data ...

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DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 24. CMOS Compatible ................................................ 81 AC Characteristic . . . . ...

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... The order number (Valid Combination) is formed by the following: S29PL127J DEVICE NUMBER/DESCRIPTION 128 Megabit ( 16-Bit), 64 Megabit ( 16-Bit), 32 Megabit ( 16-Bit) CMOS Flash Memory, Simultaneous Read/Write, Page Mode Flash Memory, 3.0 Volt-only Read, Program, and Erase Valid Combination configuration planned to be supported for this device. March 15, 2004 31107A5 ...

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Mb Products Based on 110 nm Floating Gate Technology Valid Combinations BGA Packages Package Marking S29PL129J55BAI00 PL129J55BAI00 S29PL129J55BAW00 PL129J55BAW00 S29PL129J60BAI00 PL129J60BAI00 S29PL129J60BAW00 PL129J60BAW00 S29PL129J70BAI00 PL129J70BAI00 S29PL129J70BAW00 PL129J70BAW00 S29PL129J65BAI01 PL129J60BAI01 S29PL129J65BAW01 PL129J60BAW01 S29PL129J70BAI01 PL129J70BAI01 S29PL129J70BAW01 PL129J70BAW01 S29PL127J55BAI00 PL127J55BAI00 S29PL127J55BAW00 PL127J55BAW00 ...

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Mb Products Based on 110 nm Floating Gate Technology Valid Combinations BGA Packages Package Marking S29PL064J55BAI12 PL064J55BAI12 S29PL064J55BAW12 PL064J55BAW12 S29PL064J60BAI12 PL064J60BAI12 S29PL064J60BAW12 PL064J60BAW12 S29PL064J70BAI12 PL064J70BAI12 S29PL064J70BAW12 PL064J70BAW12 S29PL064J55BAI13 PL064J55BAI13 S29PL064J55BAW13 PL064J55BAW13 S29PL064J60BAI13 PL064J60BAI13 S29PL064J60BAW13 PL064J60BAW13 S29PL064J70BAI13 PL064J70BAI13 S29PL064J70BAW13 PL064J70BAW13 ...

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Order Number PL129J, PL127J PL064J, PL032J PL129J, PL127J PL064J, PL032J PL129J, PL127J PL064J, PL032J PL129J, PL127J PL064J, PL032J PL129J, PL127J PL064J, PL032J Valid Combinations for BGA Packages Speed ...

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Product Selector Guide Part Number 2.7–3 Speed Option V = 2.7–3 1.65–1.95 V (PL127J and PL129J only) IO Max Access Time ACC Max CE# Access ...

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Simultaneous Read/Write Block Diagram Mux Amax–A0 RY/BY# Amax–A0 RESET# STATE WE# CONTROL CE# & WP#/ACC COMMAND REGISTER DQ0–DQ15 Amax–A0 Mux Note: Amax = A22 (PL127J), A21 (PL064J), A20 (PL032J ...

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Simultaneous Read/Write Block Diagram (PL129J Mux A21–A0 RY/BY# A21–A0 RESET# STATE WE# CONTROL CE1# & CE2# COMMAND REGISTER WP#/ACC DQ0–DQ15 A21–A0 Mux Notes: 1. Amax = A21 (PL129J) March 15, 2004 31107A5 ...

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... Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (TSOP, BGA, PDIP, SSOP, PLCC). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time 80-Ball Fine-pitch BGA Top View, Balls Facing Down ...

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... Note: Pinout shown for PL127J. For PL129J, F9 (A22) = RFU, and B5 (RFU) = CE#f2. Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (TSOP, BGA, PDIP, SSOP, PLCC). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. ...

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Fine-pitch BGA A6 B6 A13 A12 WE# RESET RY/BY# WP#/ACC A17 Note: Pinout shows for PL064J. For PL032J, C4(A21 ...

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Fine-pitch BGA 7x9 mm Configuration VSS CE1#f OE RFU DQ0 H2 DQ8 For this family of products, a ...

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... Am29BDS128H, Am29BDS128G, Am29BDS640G products, which use legacy standalone packages. Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (TSOP, BGA, PDIP, SSOP, PLCC). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time ...

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Pin Description Amax–A0 DQ15–DQ0 CE# OE# WE RY/BY# WP#/ACC RESET# CE1#, CE2# Notes: 1. Amax = A22 (PL127J), A21 (PL129J and PL064J), A20 (PL032J) Logic Symbol March 15, 2004 31107A5 ...

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Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used ...

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Requirements for Reading Array Data To read array data from the outputs, the system must drive the OE# and appro- priate CE# pins (For PL129J - CE1#/CE2# pins CE2# are the power control and select the lower (CE1#) ...

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Word 6 Word 7 Simultaneous Read/Write Operation In addition to the conventional features (read, program, erase-suspend read, and erase-suspend program), the device is capable of reading data from one bank of memory while a program or erase operation is in ...

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... Characteristics” CC3 Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The de- vice automatically enables this mode when addresses remain stable for t 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# con- trol signals. Standard address access timings provide new data when addresses are changed ...

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... V IL The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin re- mains a “ ...

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Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 ...

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Table 5. PL127J Sector Architecture (Continued) Bank Sector SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 ...

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Table 5. PL127J Sector Architecture (Continued) Bank Sector SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 ...

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Table 5. PL127J Sector Architecture (Continued) Bank Sector SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 SA142 SA143 SA144 SA145 SA146 SA147 SA148 SA149 SA150 ...

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Table 5. PL127J Sector Architecture (Continued) Bank Sector SA159 SA160 SA161 SA162 SA163 SA164 SA165 SA166 SA167 SA168 SA169 SA170 SA171 SA172 SA173 SA174 SA175 SA176 SA177 SA178 SA179 SA180 SA181 SA182 SA183 SA184 SA185 SA186 SA187 SA188 SA189 SA190 ...

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Table 5. PL127J Sector Architecture (Continued) Bank Sector SA199 SA200 SA201 SA202 SA203 SA204 SA205 SA206 SA207 SA208 SA209 SA210 SA211 SA212 SA213 SA214 SA215 SA216 SA217 SA218 SA219 SA220 SA221 SA222 SA223 SA224 SA225 SA226 SA227 SA228 SA229 SA230 ...

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Table 5. PL127J Sector Architecture (Continued) Bank Sector SA231 SA232 SA233 SA234 SA235 SA236 SA237 SA238 SA239 SA240 SA241 SA242 SA243 SA244 SA245 SA246 SA247 SA248 SA249 SA250 SA251 SA252 SA253 SA254 SA255 SA256 SA257 SA258 SA259 SA260 SA261 SA262 ...

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Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 ...

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Table 6. PL064J Sector Architecture (Continued) Bank Sector SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 ...

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Table 6. PL064J Sector Architecture (Continued) Bank Sector SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 ...

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Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 ...

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Table 7. PL032J Sector Architecture (Continued) Bank Sector SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 ...

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Bank Sector CE1# SA1-0 SA1-1 SA1-2 SA1-3 SA1-4 SA1-5 SA1-6 SA1-7 SA1-8 SA1-9 SA1-10 SA1-11 SA1-12 SA1-13 SA1-14 SA1-15 SA1-16 SA1-17 SA1-18 SA1-19 SA1-20 SA1-21 SA1-22 SA1-23 SA1-24 SA1-25 SA1-26 SA1-27 SA1-28 SA1-29 SA1-30 SA1-31 SA1-32 SA1-33 SA1-34 SA1-35 SA1-36 ...

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Table 8. S29PL129J Sector Architecture (Continued) Bank Sector CE1# SA1-39 SA1-40 SA1-41 SA1-42 SA1-43 SA1-44 SA1-45 SA1-46 SA1-47 SA1-48 SA1-49 SA1-50 SA1-51 SA1-52 SA1-53 SA1-54 SA1-55 SA1-56 SA1-57 SA1-58 SA1-59 SA1-60 SA1-61 SA1-62 SA1-63 SA1-64 SA1-65 SA1-66 SA1-67 SA1-68 SA1-69 ...

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Table 8. S29PL129J Sector Architecture (Continued) Bank Sector CE1# SA1-83 SA1-84 SA1-85 SA1-86 SA1-87 SA1-88 SA1-89 SA1-90 SA1-91 SA1-92 SA1-93 SA1-94 SA1-95 SA1-96 SA1-97 SA1-98 SA1-99 SA1-100 SA1-101 SA1-102 SA1-103 SA1-104 SA1-105 SA1-106 SA1-107 SA1-108 SA1-109 SA1-110 SA1-111 SA1-112 SA1-113 ...

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Table 8. S29PL129J Sector Architecture (Continued) Bank Sector CE1# SA1-127 SA1-128 SA1-129 SA1-130 SA1-131 SA1-132 SA1-133 SA1-134 SA2-0 SA2-1 SA2-2 SA2-3 SA2-4 SA2-5 SA2-6 SA2-7 SA2-8 SA2-9 SA2-10 SA2-11 SA2-12 SA2-13 SA2-14 SA2-15 SA2-16 SA2-17 SA2-18 SA2-19 SA2-20 SA2-21 SA2-22 ...

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Table 8. S29PL129J Sector Architecture (Continued) Bank Sector CE1# SA2-36 SA2-37 SA2-38 SA2-39 SA2-40 SA2-41 SA2-42 SA2-43 SA2-44 SA2-45 SA2-46 SA2-47 SA2-48 SA2-49 SA2-50 SA2-51 SA2-52 SA2-53 SA2-54 SA2-55 SA2-56 SA2-57 SA2-58 SA2-59 SA2-60 SA2-61 SA2-62 SA2-63 SA2-64 SA2-65 SA2-66 ...

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Table 8. S29PL129J Sector Architecture (Continued) Bank Sector CE1# SA2-80 SA2-81 SA2-82 SA2-83 SA2-84 SA2-85 SA2-86 SA2-87 SA2-88 SA2-89 SA2-90 SA2-91 SA2-92 SA2-93 SA2-94 SA2-95 SA2-96 SA2-97 SA2-98 SA2-99 SA2-100 SA2-101 SA2-102 SA2-103 SA2-104 SA2-105 SA2-106 SA2-107 SA2-108 SA2-109 SA2-110 ...

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Table 8. S29PL129J Sector Architecture (Continued) Bank Sector CE1# SA2-124 SA2-125 SA2-126 SA2-127 SA2-128 SA2-129 SA2-130 SA2-131 SA2-132 SA2-133 SA2-134 Factory-Locked Area Customer-Lockable Area Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier ...

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Table 10. Autoselect Codes (High Voltage Method) Description CE# OE# WE# Manufacturer ID: Spansion products Read L Cycle 1 Read L Cycle Read L Cycle 3 Sector Protection Verification SecSi Indicator ...

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Table 12. PL127J Boot Sector/Sector Block Addresses for Protection/Unprotection Sector A22-A12 SA0 00000000000 SA1 00000000001 SA2 00000000010 SA3 00000000011 SA4 00000000100 SA5 00000000101 SA6 00000000110 SA7 00000000111 SA8 00000001XXX SA9 00000010XXX SA10 00000011XXX SA11-SA14 000001XXXXX SA15-SA18 000010XXXXX SA19-SA22 000011XXXXX SA23-SA26 ...

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Table 13. PL129J Boot Sector/Sector Block Addresses for Protection/Unprotection CE1# Control Sector Group A21-12 SA1-0 0000000000 SA1-1 0000000001 SA1-2 0000000010 SA1-3 0000000011 SA1-4 0000000100 SA1-5 0000000101 SA1-6 0000000110 SA1-7 0000000111 SA1-8 0000001XXX SA1-9 0000010XXX SA1-10 0000011XXX SA1-11 - SA1-14 00001XXXXX ...

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Table 14. PL064J Boot Sector/Sector Block Addresses for Protection/Unprotection Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11-SA14 SA15-SA18 SA19-SA22 SA23-SA26 SA27-SA30 SA31-SA34 SA35-SA38 SA39-SA42 SA43-SA46 SA47-SA50 SA51-SA54 SA55-SA58 SA59-SA62 SA63-SA66 SA67-SA70 SA71-SA74 SA75-SA78 SA79-SA82 SA83-SA86 ...

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Table 15. PL032J Boot Sector/Sector Block Addresses for Protection/Unprotection Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11-SA14 SA15-SA18 SA19-SA22 SA23-SA26 SA27-SA30 SA31-SA34 SA35-SA38 SA39-SA42 SA43-SA46 SA47-SA50 SA51-SA54 SA55-SA58 SA59-SA62 SA63-SA66 SA67 SA68 SA69 SA70 SA71 ...

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DYB PPB Sector Protection The PL127J, PL129J, PL064J, and PL032J features several levels of sector protec- tion, which can disable both the program and ...

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... The device erases all PPBs in parallel. If any PPB requires erasure, the device must be instructed to preprogram all of the sector PPBs prior to PPB erasure. Oth- erwise, a previously erased sector PPBs can potentially be over-erased. The flash device does not have a built-in means of preventing sector PPBs over-erasure. ...

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Dynamic Locked or Unlocked states. They are called dynamic states be- cause it is very easy to switch back and forth between the protected and unprotected conditions. This allows software to easily protect sectors against in- advertent changes yet ...

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... The flash device internally compares the given password with the pre-programmed password. If they match, the PPB Lock bit is cleared, and the PPBs can be altered. If they do not match, the flash device does nothing. There is a built-in 2 µs delay for each “password check.” This delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password ...

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... If the system asserts V erase functions in the two outermost 4 Kword sectors on both ends of the flash array independent of whether it was previously protected or unprotected. If the system asserts V and lower two sectors to whether they were last set to be protected or unpro- tected ...

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Password Unlock command. Successful execution of the Password Unlock command clears the PPB Lock Bit, allowing for sector PPBs modifications. Assert- ing RESET#, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets ...

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START PLSCNT = 1 RESET Wait 4 µs No First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address with A7-A0 = 00000010 Wait 100 µs ...

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... Figure 2. Temporary Sector Unprotect Operation SecSi™ (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN) The 128-word SecSi sector is divided into 64 factory-lockable words that can be programmed and locked by the customer ...

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SecSi Sector Factory-locked Indicator Bit (DQ7) is permanently set to a “1”. Op- tional Spansion programming services can program the factory-locked area with a random ESN, a customer-defined code, or any combination of the two. Because only FASL can program ...

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Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes. In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious ...

Page 59

... Common Flash Memory Interface (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified soft- ware algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and back- ward-compatible for the specified flash device families ...

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... Max. timeout for full chip erase 2 Table 19. Device Geometry Definition N Device Size = 2 byte Flash Device Interface description (refer to CFI publication 100) Max. number of byte in multi-byte write = 2 (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) ...

Page 61

Table 20. Primary Vendor-Specific Extended Query Addresses Data 40h 0050h 41h 0052h 42h 0049h 43h 0031h 44h 0033h 45h TBD 46h 0002h 47h 0001h 48h 0001h 49h 0007h (PLxxxJ) 00E7h (PL127J) 00E7h (PL129J) 4Ah 0077h (PL064J) 003Fh (PL032J) 4Bh 0000h ...

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Table 20. Primary Vendor-Specific Extended Query (Continued) Addresses Data 0060h (PL127J) 0060h (PL129J) 5Ah 0030h (PL064J) 0018h (PL032J) 0027h (PL127J) 0027h (PL129J) 5Bh 0017h (PL064J) 000Fh (PL032J Description ...

Page 63

Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A ...

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... Embedded Program or embedded Erase algorithm. Table 21 sequences. See also “SecSi™ (Secured Silicon) Sector Flash Memory Region” for further information. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled. ...

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The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. Note that the SecSi Sec- tor, autoselect and CFI functions are unavailable when the SecSi Sector is enabled. Programming ...

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Increment Address Note: See Table 21 Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is ini- tiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write ...

Page 67

Refer to the Operations" section tables in the AC Characteristics section for parameters, and Figure 16 section for timing diagrams. Sector Erase Command Sequence Sector erase is a six bus cycle operation. ...

Page 68

Notes: 1. See Table 21 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer. Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation ...

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DQ7 or DQ6 status bits, just as in the standard Word Program operation. Refer to the information. In the erase-suspend-read mode, the system can also issue the autoselect com- mand sequence. The device allows reading autoselect codes ...

Page 70

Command Definitions Tables Table 21. Memory Array Command Definitions Command (Notes) Read (Note 5) 1 Reset (Note 6) 1 Manufacturer ID 4 Device ID (Note 10) 6 Autoselect (Note 7) SecSi Sector Factory 4 Protect (Note 8) Sector Group Protect ...

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System may read and program in non-erasing sectors, or enter autoselect mode, when in Program/Erase Suspend mode. Program/Erase Suspend command is valid only during a sector erase operation, and requires bank address. 12. Program/Erase Resume command is valid only ...

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Table 22. Sector Protection Command Definitions Command (Notes) Addr Data Addr Data Addr Data Reset 1 XXX F0 SecSi Sector 3 555 AA 2AA Entry SecSi Sector 4 555 AA 2AA Exit SecSi Protection Bit 6 555 AA 2AA Program ...

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RD(1) = Read Data DQ1 for PPB Lock status Sector Address where security command applies. Address bits Amax:A12 uniquely select any sector Persistent Protection Mode Lock Address (A7:A0) is (00010010 PPB Address (A7:A0) is ...

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After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 400 µs, then the bank returns to the read mode. If not all selected sectors are protected, ...

Page 75

RY/BY#: Ready/Busy# The RY/BY dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since ...

Page 76

Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the "DQ2: Toggle Bit II" section for more information. DQ2: Toggle Bit II The ...

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Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with ...

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Status Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Erase Suspended Sector Erase-Suspend- Erase Read Suspend Non-Erase Mode Suspended Sector Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing ...

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Absolute Maximum Ratings Storage Temperature Plastic Packages . . . . . . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . ...

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Operating Ranges Operating ranges define those limits between which the functionality of the de- vice is guaranteed. Industrial (I) Devices Ambient Temperature (T Extended (E) Devices Ambient Temperature (T Supply Voltages ...

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DC Characteristics Parameter Parameter Description Symbol I Input Load Current LI I A9, OE#, RESET# Input Load Current LIT I Reset Leakage Current LR I Output Leakage Current Active Read Current (Notes 1, 2) CC1 CC I ...

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AC Characteristic Test Conditions Device Under Test 3 Note: Diodes are IN3064 or equivalent Output Load Output Load Capacitance, C (including jig capacitance) L Input Rise and Fall Times Input Pulse Levels Input timing ...

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SWITCHING WAVEFORMS Table 26. KEY TO SWITCHING WAVEFORMS WAVEFORM Don’t Care, Any Change Permitted VIO In VIO/2 0.0 V Figure 10. Input Waveforms and Measurement Levels VCC RampRate All DC characteristics are specified for a V >=V - 100 mV. ...

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Read Operations Parameter JEDEC Std. Description t t Read Cycle Time (Note AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV CE t Page Access Time PACC t t Output Enable ...

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Addresses CE# OE# WE# Data RESET# RY/BY Notes: 1. S29PL129J - During CE1# transitions, CE2 S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2# Amax-A3 A2-A0 Data ...

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Reset Parameter JEDEC Std RESET# Pin Low (During Embedded Algorithms) t Ready to Read Mode (See Note) RESET# Pin Low (NOT During Embedded t Ready Algorithms) to Read Mode (See Note) t RESET# Pulse Width RP t Reset High Time ...

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Erase/Program Operations Parameter JEDEC Std Description t t Write Cycle Time AVAV Address Setup Time AVWL AS Address Setup Time to OE# low during toggle bit t ASO polling t t Address Hold Time WLAX AH Address ...

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Timing Diagrams Program Command Sequence (last two cycles Addresses 555h CE# OE# WE Data RY/BY VCS Notes program address program data S29PL129J - During CE1# transitions, ...

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Erase Command Sequence (last two cycles Addresses 2AAh CE# OE# WE Data RY/BY# t VCS V CC Notes sector address (for Sector Erase Valid Address for reading status data (see “Write ...

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Addresses t ACC OE# t OEH WE# DQ7 DQ6–DQ0 t BUSY RY/BY# Note Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle Figure ...

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Enter Erase Embedded Suspend Erasing Erase Erase Suspend WE# DQ6 DQ2 Note:Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6. Protect/Unprotect Parameter JEDEC Std ...

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RESET# SA, A6, A1, A0 Sector Group Protect/Unprotect Data 60h 1 µs CE# WE# OE# Notes: 1. For sector protect For sector unprotect ...

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Controlled Erase Operations Table 31. Alternate CE# Controlled Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time AVAV Address Setup Time AVWL Address Hold Time ELAX Data ...

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Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a program or erase operation program address, ...

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CE1# CE2# Figure 23. Timing Diagram for Alternating Between CE1# and CE2# Control Table 34. Erase And Programming Performance Parameter Sector Erase Time PL127J/129J Chip Erase Time PL064J PL032J Word Program Time Accelerated Word Program Time PL127J/129J Chip Program Time ...

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Physical Dimensions VBG080—80-Ball Fine-pitch Ball Grid Array Package (PL127J and PL129J) 0. (2X) INDEX MARK PIN A1 CORNER 10 TOP VIEW A A1 SIDE VIEW PACKAGE VBG 080 JEDEC N/A 11. 8.00 ...

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VBH064—64-Ball Fine-pitch Ball Grid Array 8 x 11.6 mm package (PL127J) 0. (2X) A1 CORNER INDEX MARK 10 TOP VIEW A A1 SIDE VIEW PACKAGE VBH 064 JEDEC N/A 11. 8.00 mm NOM PACKAGE SYMBOL MIN ...

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VBK048— mm, 48-ball Fine pitch BGA (PL064J/PL032J) D INDEX MARK PIN A1 CORNER 10 TOP VIEW A SEATING PLANE A1 SIDE VIEW PACKAGE VBK 048 JEDEC N/A 8. 6.15 mm NOM PACKAGE SYMBOL MIN NOM MAX ...

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Revision Summary Revision A (January 29, 2004) Initial release. Revision A+1 (February 12, 2004) Software Features Included backward compatibility with MBM29xx families. General Description 48-ball BGA package is not supported and was removed. Ordering Information Model numbers for the 48-ball ...

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... Copyright © 2004 FASL LLC. All rights reserved. Spansion, the Spansion logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of FASL LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies. ...

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