SL811HST Cypress Semiconductor Corp, SL811HST Datasheet - Page 9

• Manufacturer Part Number: SL811HST
• Manufacturer: Cypress Semiconductor Corp

Specifications of SL811HST

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: PLCC
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

3.1.3.2 Interrupt Enable Register [Address = 06h]
The SL811HS provides an Interrupt Request Output, which
can be activated for a number of conditions. The Interrupt
Enable Register allows the user to select conditions that will
result in an Interrupt being issued to an external CPU via the
INTRQ pin. A separate Interrupt Status Register reflects the
reason for the interrupt. Enabling or disabling these interrupts
does not have an effect on whether or not the corresponding
bit in the Interrupt Status Register will be set or cleared, it only
determines if the interrupt will be routed to the INTRQ pin. The
Table 3-13. Interrupt Enable Register [Address 06h]
3.1.3.3 USB Address Register, Reserved, Address [Address = 07h]
This register is reserved for the device USB Address in Slave operation. It should not be written by the user in host mode.
3.1.3.4 Registers 08h-0Ch Host-B registers
Registers 08h-0Ch have the same definition as registers 00h-04h except they apply to Host-B instead of Host-A.
3.1.3.5 Interrupt Status Register, Address [Address = 0Dh]
The Interrupt Status Register is a Read/Write register providing interrupt status. Interrupts can be cleared by writing to this register.
To clear a specific interrupt, the register is written with corresponding bit set to “1.”
Table 3-14. Interrupt Status Register [Address 0Dh]
Document 38-08008 Rev. *B
Bit Position
Bit Position
Reserved
Bit 7
Bit 7
D+
7
6
5
4
3
2
1
0
7
Detect/Resume
Device Detect/Resume Enable Device Detect/Resume Interrupt.
Inserted/Removed
SOF Timer
Reserved
Reserved
USB-B DONE
USB-A DONE
Detect/Resume
Bit Name
D+
Device
Device
Bit 6
Bit 6
Bit Name
Reserved
Insert/Remove
Removed
Inserted/
Bit 5
Bit 5
Function
0
When bit-6 of register 05h (Control Register 1) is equal to “1,” bit 6 of this register
enables the Resume Detect Interrupt. Otherwise, this bit is used to enable Device
detection status as defined in the Interrupt Status Register bit definitions.
Enable Slave Insert/Remove Detection - used to enable/disable the device
inserted/removed interrupt.
1 = Enable Interrupt for SOF Timer. This is typically at 1mS intervals although the timing
is determined by the SOF Counter high/low registers.
To utilize this bit function, bit 0 of register 05h must be enabled and the SOF counter
registers 0Ehand 0Fh must be initialized.
0
0
USB-B Done Interrupt. (see USB-A Done interrupt).
USB-A Done Interrupt. The Done interrupt is triggered by one of the events that will be
logged in the USB Packet Status register. The Done interrupt will cause the Packet
Status Register to be updated.
Function
Value of the Data+ Pin.
Bit 7 provides continuous USB Data+ line status. Once it has been determined that a
device has been inserted as described below with bits 5 and 6, bit 7 can be used to
detect if the inserted device is low-speed (0) or full-speed (1).
SOF Timer
SOF timer
Bit 4
Bit 4
Interrupt Status Register is normally used in conjunction with
the Interrupt Enable Register and can be polled in order to
determine the conditions that initiated the interrupt (See
Interrupt Status Register description). When a bit is set to “1”
the corresponding interrupt is enabled, so when the enabled
interrupt occurs, the INTRQ pin will be asserted. The INTRQ
pin is a level interrupt, meaning it will not be deasserted until
all enabled interrupts are cleared.
Reserved
Reserved
Bit 3
Bit 3
Reserved
Reserved
Bit 2
Bit 2
USB-B
USB-B
DONE
Bit 1
Bit 1
SL811HS
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USB-A
USB-A
DONE
Bit 0
Bit 0
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