SL811HST Cypress Semiconductor Corp, SL811HST Datasheet - Page 15

• Manufacturer Part Number: SL811HST
• Manufacturer: Cypress Semiconductor Corp

Specifications of SL811HST

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: PLCC
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

Table 3-29. J-K Force-state Control Bits
3.2.4.2 Interrupt Enable Register, Address [06h]
The SL811HS provides an Interrupt Request Output that is activated resulting from a number of conditions. The Interrupt Enable
Register allows the user to select events that will generate the Interrupt Request Output assertion. A separate Interrupt Status
Register can be read in order to determine the condition that initiated the interrupt (See Interrupt Status Register description
Section 3.2.4.4). When a bit is set to 1, the corresponding interrupt is enabled. Setting a bit in the Interrupt Enable Register does
not effect the Interrupt Status register’s value, it just determines which interrupts will be output on INTRQ.
Table 3-30. Interrupt Enable Register [Address: 06h]
3.2.4.3 USB Address Register, Address [07h]
This register contains the USB Device Address after assignment by USB Host during configuration. On power up or Reset, USB
Address Register is set to Address 00h. After USB configuration and address assignment, the device will recognize only USB
transactions directed to the address contained in the USB Address Register.
Table 3-31. USB Address Register [Address 07h]
Document 38-08008 Rev. *B
JK-Force State
Bit Position Bit Name
Bit Position Bit Name
DMA Status
USBADD7
4
3
2
1
0
7
6
5
4
3
2
1
0
7
7
0
0
1
1
J-K1
J-K0
DMA Dir
DMA Enable
USB Enable
DMA Status
USB Reset
SOF Received
DMA Done
Endpoint 3 Done
Endpoint 2 Done
Endpoint 1 Done
Endpoint 0 Done
USB Reset
USBADD6
USB Engine Reset
6
6
0
1
0
1
USBADD5
Received
Function
J-K1 and J-K0 force state control bits can be used to generate various USB bus conditions.
Forcing K-state can be used for Peripheral device remote wake-up, Resume and other
modes. These two bits are set to zero on power up see Table 3-29 for functions.
DMA transfer direction bit. Set equal to 1 for DMA read cycles from SL811HS, Set equal to
0 for DMA write cycles.
Enable DMA Operation when equal to 1. Disable = 0. DMA is initiated when DMA Count
High is written.
Overall Enable for transfers. 1 enables and 0 disables. This bit should be set to 1 to enable
USB communication. Default at power on = 0
Function
When equal to 1, indicates DMA transfer is in progress; When equal to 0, indicates DMA
transfer is complete.
Enable USB Reset received interrupt when = 1.
Enable SOF Received Interrupt when = 1.
Enable DMA done Interrupt when = 1.
Enable Endpoint 3 done Interrupt when = 1.
Enable Endpoint 2 done Interrupt when = 1.
Enable Endpoint 1 done Interrupt when = 1.
Enable Endpoint 0 done Interrupt when = 1.
SOF
5
5
Normal operating mode
Force SE0, D+ and D– are set low
Force K-State, D– set high, D+ set low
Force J-State, D+ set high, D– set low
DMA Done
USBADD4
4
4
Function
Endpoint 3
USBADD3
Done
3
3
Endpoint 2
USBADD2
Done
2
2
Endpoint 1
USBADD1
Done
1
1
SL811HS
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Endpoint 0
USBADD0
Done
0
0
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