SSTUB32S869BHLF IDT, Integrated Device Technology Inc, SSTUB32S869BHLF Datasheet - Page 5

• Manufacturer Part Number: SSTUB32S869BHLF
• Description: IC REGIST BUFF 14BIT DDR2 150BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Bufferr

Specifications of SSTUB32S869BHLF

• Tx/rx Type: LVCMOS
• Delay Time: 3.0ns
• Capacitance - Input: 3.5pF
• Voltage - Supply: 1.7 V ~ 1.9 V
• Mounting Type: Surface Mount
• Package / Case: *
• Logic Family: SSTU
• Logical Function: Reg Bfr W/ParityTst
• Number Of Elements: 1
• Number Of Bits: 14
• Number Of Inputs: 14
• Number Of Outputs: 28
• High Level Output Current: -16mA
• Low Level Output Current: 16mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 340(Min)MHz
• Mounting: Surface Mount
• Pin Count: 150
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Compliant

Terminal Functions
NOTE 1 Inputs D1, D4 and D7 and their corresponding outputs Qn are not included in this range.
1203—04/11/06
Ungated inputs DCKE, DODT
Chip Select
gated inputs
Chip Select
inputs
Re-driven
outputs
Parity input
Parity output
Parity error
output
Configuration
Inputs
Clock inputs
Miscellaneous
inputs
Signal Group
D1 ... D14
DC
Q1A...Q14A,
Q1B ... Q14B,
QCSA#, QCSB#
QCKEA,QCKEB
QODTA,QODTB
PARIN1
PPO1
PTYERR1#
C1
CK, CK#
RESET#
VREF
VDD
GND
Signal Name
(1)
SSTL_18
SSTL_18
SSTL_18
SSTL_18
SSTL_18
SSTL_18
Open drain
1.8V
LVCMOS
SSTL_18
1.8 V
LVCMOS
0.9 V nominal Input reference voltage for the SSTL_18 inputs. Two pins
Power Input
Ground Input Ground
Type
DRAM function pins not associated with Chip Select.
DRAM inputs, re-driven only when Chip Select is LOW.
DRAM Chip Select signals. This pins initiate DRAM address/
command decodes, and as such at least one will be low when
a valid address/command is present.
Outputs of the register, valid after the specified clock count
and immediately following a rising edge of the clock.
Inout parity is received on pin PARIN1 and should maintain
parity across the D1...D14
clock, one cycle after Chip Select is LOW.
Partial Parity Output. Indicates parity out of D1-D14
When LOW, this output indicates that a parity error was
identified associated with the address and/or command inputs.
PTYERR1# will be active for two clock cycles, and delayed
by in total 2 clock cycles for compatibility with final parity
out timing on the industry-standard DDR2 register with
parity (in JEDEC definition).
When Low, register is configured as Register 1. When High,
register is confugured as Register 2.
Differential master clock input pair to the register. The
register operation is triggered by a rising edge on the positive
clock input (CK).
Asynchronous reset input. When LOW, it causes a reset of the
internal latches, thereby forcing the outputs LOW. RESET#
also resets the PTYERR# signal.
(internally tied together) are used for increased reliability.
Power supply voltage
5
Description
(1)
inputs, at the rising edge of the
ICSSSTUB32S869B
Advance Information
(1)