SSTUB32S869BHLF IDT, Integrated Device Technology Inc, SSTUB32S869BHLF Datasheet - Page 4

• Manufacturer Part Number: SSTUB32S869BHLF
• Description: IC REGIST BUFF 14BIT DDR2 150BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Bufferr

Specifications of SSTUB32S869BHLF

• Tx/rx Type: LVCMOS
• Delay Time: 3.0ns
• Capacitance - Input: 3.5pF
• Voltage - Supply: 1.7 V ~ 1.9 V
• Mounting Type: Surface Mount
• Package / Case: *
• Logic Family: SSTU
• Logical Function: Reg Bfr W/ParityTst
• Number Of Elements: 1
• Number Of Bits: 14
• Number Of Inputs: 14
• Number Of Outputs: 28
• High Level Output Current: -16mA
• Low Level Output Current: 16mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 340(Min)MHz
• Mounting: Surface Mount
• Pin Count: 150
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Compliant

ICSSSTUB32S869B
Advance Information
General Description
The ICSSSTUB32S869B is 14-bit 1:2 registered buffer with parity is designed for 1.7 V to 1.9 V VDD operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All
outputs are 1.8 V CMOS drivers optimized to drive the DDR2 DIMM load. They provide 50% more dynamic driver
strength than the standard SSTU32864 outputs.
The ICSSSTUB32S869B operates from a differential clock (CK and CK). Data are registered at the crossing of CK going
high, and CK going low.
The device supports low-power standby operation. When the reset input (RESET) is low, the differential input receivers
are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when
RESET is low all registers are reset, and all outputs except PTYERR1# are forced low. The LVCMOS RESET input must
always be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low
state during power up.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CK and CK.
Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared
and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers.
ICSSSTUB32S869B must ensure that the outputs remain low as long as the data inputs are low, the clock is stable
during the time from the low-to-high transition of RESET and the input receivers are fully enabled. This will ensures that
there are no glitches on the output.
The device monitors both DCS and CSR inputs and will gate the Qn, PPO1 (Paritial-Parity-Out) and PTYERR1# (Parity
Error) Parity outputs from changing states when both DCS and CSR are high. If either DCS or CSR input is low, the
Qn, PPO1 and PTYERR1# outputs will function normally. The RESET input has priority over the DCS and CSR controls
and will force the Qn and PPO outputs low and the PTYERR1# high.
The ICSSSTUB32S869B includes a parity checking function. The ICSSSTUB32S869B accepts a parity bit from the
memory controller at its input pin PARIN1 one or two cycles after the corresponding data input, compares it with the
data received on the D-inputs and indicates on its opendrain PTYERR1 pin (active low) whether a parity error has
occurred. The number of cycles depends on the setting of C1, see Figure 6 and 7.
When used as a single device, the C1 input is tied low. When used in pairs, the C1 inputs is tied low for the first register
(front) and the C1 input is tied high for the second register. When used as a single register, the PPO1 and PTYERR1#
signals are produced two clock cycles after the corresponding data input. When used in pairs, the PTYERR1# signals
of the first register are left floating. The PPO1 outputs of the first register are cascaded to the PARIN1 signals on the
second register (back). The PPO1 and PTYERR1# signals of the second register are produced three clock cycles after
the corresponding data input. Parity implimentation and device wiring for single and dual die is described in Figure 1.
If an error occurs, and the PTYERR1# is driven low, it stays low for two clock cycles or until RESET is driven low. The
DIMM-dependent signals (DCKE, DCS, CSR and DODT) are not included in the parity check computations.
All registers used on an individual DIMM must be of the same configuration, i.e single or dual die.
Parin1, W4
PTYERR1# W1
PPO1, W8
Parin1, W4
.
.
Register 1
Register 2
Parin
(Front)
(Back)
NC, A4
NC, A8
NC, A1 1
NC, A8
Set C1 = 0 for Register 1; Set C1 = 1 for Register 2. NC denotes No Connect.
Figure 1 — Parity implementation and device wiring for SSTU32S869 and SSTU32D869
1203—04/11/06
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