SSTUB32S869BHLF IDT, Integrated Device Technology Inc, SSTUB32S869BHLF Datasheet - Page 15

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SSTUB32S869BHLF

Manufacturer Part Number
SSTUB32S869BHLF
Description
IC REGIST BUFF 14BIT DDR2 150BGA
Manufacturer
IDT, Integrated Device Technology Inc
Type
Bufferr
Datasheet

Specifications of SSTUB32S869BHLF

Tx/rx Type
LVCMOS
Delay Time
3.0ns
Capacitance - Input
3.5pF
Voltage - Supply
1.7 V ~ 1.9 V
Mounting Type
Surface Mount
Package / Case
*
Logic Family
SSTU
Logical Function
Reg Bfr W/ParityTst
Number Of Elements
1
Number Of Bits
14
Number Of Inputs
14
Number Of Outputs
28
High Level Output Current
-16mA
Low Level Output Current
16mA
Propagation Delay Time
3ns
Operating Supply Voltage (typ)
1.8V
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Clock-edge Trigger Type
Posit/Negat-Edge
Polarity
Non-Inverting
Technology
CMOS
Frequency (max)
340(Min)MHz
Mounting
Surface Mount
Pin Count
150
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SSTUB32S869BHLF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
SSTUB32S869BHLFT
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
1203—04/11/06
Error output load circuit and voltage measurement information (V
All input pulses are supplied by generators having the following characteristics: PRR 10 MHz;
Z
(1) C
Figure 17 — Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to RESET#
o
Figure 18 — Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect to clock
Figure 19 — Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to clock
= 50 ; input slew rate = 1 V/ns ± 20%, unless otherwise specified.
L
includes probe and jig capacitance.
Figure 16 — Load circuit, error output measurements
Waveform 2
Waveform 1
Waveform 2
LVCMOS
Timing
Output
Timing
Output
Inputs
Inputs
RESET
Output
Input
t PLH
DUT
OUT
V ICR
t HL
V ICR
t LH
V CC /2
0.15 V
15
inputs
inputs
V CC /2
input
0.15 V
SEE NOTE (1)
C L = 10 pF
V ICR
V ICR
V DD
R L = 1 k
TEST POINT
002aaa500
002aaa502
002aaa503
002aaa501
DD
ICSSSTUB32S869B
Advance Information
V CC
V OL
V OH
0 V
V I(PP)
V I(PP)
V CC
0 V
V OH
0 V
= 1.8 V ± 0.1 V)

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