P82B96TD,118 NXP Semiconductors, P82B96TD,118 Datasheet - Page 16

• Manufacturer Part Number: P82B96TD,118
• Description: IC I2C BUS BUFFER DUAL 8-SOIC
• Manufacturer: NXP Semiconductors
• Type: Bufferr

Specifications of P82B96TD,118

• Package / Case: 8-SOIC (3.9mm Width)
• Tx/rx Type: I²C Logic
• Delay Time: 5.0ns
• Capacitance - Input: 7pF
• Voltage - Supply: 2 V ~ 15 V
• Current - Supply: 900µA
• Mounting Type: Surface Mount
• Number Of Channels Per Chip: Dual
• Supply Voltage (max): 15 V
• Supply Voltage (min): 2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Logic Type: Bidirectional Bus Buffer
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: OM6285 - EVAL BOARD I2C-2002-1A568-4002 - DEMO BOARD I2C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-1009-2; 935262295118; P82B96TD-T

NXP Semiconductors
P82B96_8
Product data sheet
Fig 17. Rising edge of SDA at slave is delayed by the buffers and bus rise times
V
CCM
MASTER
Effective delay of SDA at master = 270 + 0.2RsCs + 0.7 (RbCb + RmCm) ns.
C = F; R = .
I
2
C-BUS
local master bus
GND (0 V)
SDA
Figure
with relatively large capacitance, linking two Fast mode I
simplified expressions for making the relevant timing calculations for 3.3 V or 5 V
operation. Because the buffers and the wiring introduce timing delays, it may be
necessary to decrease the nominal SCL frequency below 400 kHz. In most cases the
actual bus frequency will be lower than the nominal Master timing due to bit-wise
stretching of the clock periods.
The delay factors involved in calculation of the allowed bus speed are:
A — The propagation delay of the master signal through the buffers and wiring to the
slave. The important delay is that of the falling edge of SCL because this edge ‘requests’
the data or acknowledge from a slave. See
B — The effective stretching of the nominal LOW period of SCL at the master caused by
the buffer and bus rise times. See
C — The propagation delay of the slave's response signal through the buffers and wiring
back to the master. The important delay is that of a rising edge in the SDA signal. Rising
edges are always slower and are therefore delayed by a longer time than falling edges.
(The rising edges are limited by the passive pull-up while falling edges are actively driven).
See
The timing requirement in any I
provided in response to a falling edge of SCL) must be received at the master before the
end of the corresponding LOW period of SCL as appears on the bus wiring at the master.
Since all slaves will, as a minimum, satisfy the worst case timing requirements of a
400 kHz part, they must provide their response within the minimum allowed clock LOW
period of 1300 ns. Therefore in systems that introduce additional delays it is only
necessary to extend that minimum clock LOW period by any ‘effective’ delay of the slave's
response. The effective delay of the slaves response equals the total delays in SCL falling
Figure
15,
Rm
Cm
master bus
capacitance
Figure
17.
V
CCB
Sx
P82B96
16, and
Rev. 08 — 10 November 2009
Figure 17
Tx/Rx
buffered expansion bus
2
C-bus system is that a slave's data response (which is
Figure
Cb
buffered bus
wiring capacitance
Rb
show the P82B96 used to drive extended bus wiring,
Tx/Rx
16.
Figure
P82B96
15.
Sx
2
C-bus nodes. It includes
Dual bidirectional bus buffer
Rs
Cs
slave bus
capacitance
remote slave bus
SDA
© NXP B.V. 2009. All rights reserved.
I
P82B96
2
C-BUS
SLAVE
002aab993
V
CCS
16 of 32