CY8C9520A-24PVXI Cypress Semiconductor Corp, CY8C9520A-24PVXI Datasheet - Page 12

• Manufacturer Part Number: CY8C9520A-24PVXI
• Description: IC I/O EXPANDER I2C 20B 28SSOP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C9520A-24PVXI

• Package / Case: 28-SSOP
• Interface: I²C
• Number Of I /o: 20
• Interrupt Output: Yes
• Frequency - Clock: 100KHz
• Voltage - Supply: 3 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Includes: EEPROM, POR, PWM, WDT
• Processor Series: CY8C95x0A
• Core: M8C
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 20
• Operating Supply Voltage: 3 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3242-IOX, CY3242-IOXLite
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Program Memory Type: EEPROM
• Program Memory Size: 32 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 428-2023 - KIT EVAL PSOC I2C PORT EXP428-1911 - KIT EVAL PSOC I2C PORT EXP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2015-5

Int. Status Port Registers (10h - 17h)
Each ’1’ bit in these registers signals that there was a change in
the corresponding input line since the last read of that Interrupt
Status register. Each Interrupt (Int.) Status register is cleared
only after a read of that register.
If a PWM is assigned to a pin, then all state changes of the PWM
sets the corresponding bit in the Interrupt Status register. If the
pin's interrupt mask is cleared and the PWM is set to the slowest
possible rate allowed (driven by the programmable clock source
with divide register 2Dh set to FFh), then the INT line also drives
on the PWM state change.
Port Select Register (18h)
This register configures the GPort. Write a value of 0-7 to this
register to select the port to program with registers 19h-23h.
Interrupt Mask Port Register (19h)
The Interrupt Mask register enables or disables activation of the
INT line when GPIO input levels are changed. Each ’1’ in the
Interrupt Mask register masks (disables) interrupts generated
from the corresponding input line of the GPort selected by the
Port Select register (18h).
Select PWM Register (1Ah)
This register allows each port to act as a PWM output. By default,
all ports are configured as GPIO lines. Each ’1’ in this register
connects the corresponding pin of the GPort selected by the Port
Select register (18h) to the PWM output. Output register data
also affects the pin state when a PWM is enabled. See
Note that a pin used as PWM output must be configured to the
appropriate drive mode. See
mation.
Table 8
registers.
Table 8. Output and Select PWM Registers Logic
Inversion Register (1Bh)
This register can invert the logic of the input ports. Each ’1’
written to this register inverts the logic of the corresponding bit in
the Input register of the GPort selected by the Port Select register
(18h).
Document Number: 38-12036 Rev. *E
Output
describes the logic of the Output and Select PWM
0
1
0
1
Select PWM
Table 10
0
0
1
1
on page 12 for more infor-
Current PWM
Pin State
0
1
0
Table
8.
The Input registers' logic is presented in
have no effect on outputs or PWMs.
Table 9. Inversion Register Logic
Port Direction Register (1Ch)
Each bit in a port is configurable as either an input or an output.
To perform this configuration, the Port Direction register (1Ch) is
used for the GPort selected by the Port Select register (18h). If
a bit in this register is set (written with '1'), the corresponding port
pin is enabled as an input. If a bit in this register is cleared (written
with '0'), the corresponding port pin is enabled as an output.
Drive Mode Registers (1Dh-23h)
Each port's data pins can be set separately to one of seven
available modes: pull up or down, open drain high/low, strong
drive fast/slow, or high-impedance input. To perform this config-
uration, the seven drive mode registers are used for the GPort
selected by the Port Select register (18h). Each ’1’ written to this
register changes the corresponding line drive mode. Registers
1Dh through 23h have last register priority meaning that the bit
set to high in which the last register was written overrides those
that came before. Reading these registers reflects the actual
setting, not what was originally written.
Table 10. Drive Mode Register Settings
PWM Select Register (28h)
This register is configures the PWM. Write a value of 00h-0Fh to
this register to select the PWM to program with registers
29h-2Bh.
1Dh
1Eh
1Fh
20h
21h
22h
23h
Reg.
Pin State
0
1
0
1
Resistive Pull Up
Resistive Pull Down Strong High, Resistive Low
Open Drain High
Open Drain Low
Strong Drive
Slow Strong Drive
High Impedance
Pin State
CY8C9540A, CY8C9560A
Invert
0
0
1
1
Resistive High, Strong Low
(default)
Slow Strong High, High Z Low
Slow Strong Low, High Z High
Strong High, Strong Low, Fast
Output Mode
Strong High, Strong Low,
Slow Output Mode
High Z
Table
Description
CY8C9520A
Page 12 of 32
9. These registers
Input
0
1
1
0
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