CY8C9520A-24PVXI Cypress Semiconductor Corp, CY8C9520A-24PVXI Datasheet

IC I/O EXPANDER I2C 20B 28SSOP

CY8C9520A-24PVXI

Manufacturer Part Number
CY8C9520A-24PVXI
Description
IC I/O EXPANDER I2C 20B 28SSOP
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY8C9520A-24PVXI

Package / Case
28-SSOP
Interface
I²C
Number Of I /o
20
Interrupt Output
Yes
Frequency - Clock
100KHz
Voltage - Supply
3 V ~ 5.25 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Includes
EEPROM, POR, PWM, WDT
Processor Series
CY8C95x0A
Core
M8C
Data Bus Width
8 bit
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
20
Operating Supply Voltage
3 V to 5.25 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
CY3242-IOX, CY3242-IOXLite
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Program Memory Type
EEPROM
Program Memory Size
32 KB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
428-2023 - KIT EVAL PSOC I2C PORT EXP428-1911 - KIT EVAL PSOC I2C PORT EXP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-2015-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY8C9520A-24PVXI
Manufacturer:
LT
Quantity:
1 378
Part Number:
CY8C9520A-24PVXI
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Features
Top Level Block Diagram
Cypress Semiconductor Corporation
Document Number: 38-12036 Rev. *E
SDA
SCL
I
Up to 20 (CY8C9520A), 40 (CY8C9540A), or 60 (CY8C9560A)
I/O data pins independently configurable as inputs, outputs,
Bi-directional input/outputs, or PWM outputs
4/8/16 PWM sources with 8-bit resolution
Extendable soft addressing algorithm allowing flexible I
address configuration
Internal 3-/11-/27-Kbyte EEPROM
User default storage, I/O port settings in internal EEPROM
Optional EEPROM write disable (WD) input
Interrupt output indicates input pin level changes and pulse
width modulator (PWM) state changes
Internal power on reset (POR)
Internal configurable watchdog timer
V
V
2
dd
ss
C interface logic electrically compatible with SMBus
24 MHz
32 kHz
Divider (1-255)
93.75 kHz
Clocks
1.5 MHz
PWM 15
PWM 0
Power-on-Reset
WD
Settings
User
Area
EEPROM
Control
Unit
Available
User
Area
GPort 0
GPort 1
GPort 2
GPort 3
GPort 7
198 Champion Court
4 Bit IO
or A1-A3, WD6
8 Bit IO
A0
3 Bit IO
or A4-A6
8 Bit IO
5 Bit IO
8 Bit IO
INT
2
C
20, 40, and 60 Bit I/O Expander with
Overview
The CY8C95xxA is a multi-port I/O expander with on board user
available EEPROM and several PWM outputs. All devices in this
family operate identically but differ in I/O pins, number of PWMs,
and internal EEPROM size.
The CY8C95xxA operates as two I
device is a multi port I/O expander (single I
all ports through registers). The second device is a serial
EEPROM. Dedicated configuration registers can be used to
disable the EEPROM. The EEPROM uses 2-byte addressing to
support the 28 Kbyte EEPROM address space. The selected
device is defined by the most significant bits of the I
or by specific register addressing.
The I/O expander's data pins can be independently assigned as
inputs, outputs, quasi-bidirectional input/outputs or PWM ouputs.
The individual data pins can be configured as open drain or
collector, strong drive (10 mA source, 25 mA sink), resistively
pulled up or down, or high impedance. The factory default config-
uration is pulled up internally.
The system master writes to the I/O configuration registers
through the I
are storable as user defaults in a dedicated section of the
EEPROM. If user defaults were stored in EEPROM, they are
restored to the ports at power up. While this device can share the
bus with SMBus devices, it can only communicate with I
masters. The I
supports clock stretching.
There is one dedicated pin that is configured as an interrupt
output (INT) and can be connected to the interrupt logic of the
system master. This signal can inform the system master that
there is incoming data on its ports or that the PWM output state
was changed.
The EEPROM is byte readable and supports byte-by-byte
writing. A pin can be configured as an EEPROM Write Disable
(WD) input that blocks write operations when set high. The
configuration registers can also disable EEPROM operations.
The CY8C95xxA has one fixed address pin (A0) and up to six
additional pins (A1-A6), which allow up to 128 devices to share
a common two wire I
Addressing algorithm provides the option to choose the number
of pins needed to assign the desired address. Pins not used for
address bits are available as GPIO pins.
There are 4 (CY8C9520A), 8 (CY8C9540A), or 16 (CY8C9560A)
independently configurable 8-bit PWMs. These PWMs are listed
as PWM0-PWM15. Each PWM can be clocked by one of six
available clock sources.
For details on how to configure I
"Communication - I
AN2304" at
San Jose
http://www.cypress.com.
2
C bus. Configuration and output register settings
2
C slave in this device requires that the I
CY8C9540A, CY8C9560A
2
,
C Port Expander with Flash Storage -
CA 95134-1709
2
C data bus. The Extendable Soft
Revised December 14, 2010
2
2
C slave devices. The first
C, see Application Note
CY8C9520A
2
EEPROM
C address to access
•408-943-2600
2
C address
2
C master
2
C
[+] Feedback

Related parts for CY8C9520A-24PVXI

CY8C9520A-24PVXI Summary of contents

Page 1

... Features 2 ■ interface logic electrically compatible with SMBus ■ (CY8C9520A), 40 (CY8C9540A (CY8C9560A) I/O data pins independently configurable as inputs, outputs, Bi-directional input/outputs, or PWM outputs ■ 4/8/16 PWM sources with 8-bit resolution ■ Extendable soft addressing algorithm allowing flexible I address configuration ■ Internal 3-/11-/27-Kbyte EEPROM ■ ...

Page 2

... Thermal Impedances ........................................23 Solder Reflow Peak Temperature ....................23 Features and Ordering Information .....................24 Ordering Code Definitions ................................24 Acronyms ...............................................................25 Reference Documents ..........................................25 Document Conventions ........................................25 Units of Measure ..............................................25 Numeric Conventions .......................................25 Glossary .................................................................26 Document History Page ........................................31 Sales, Solutions, and Legal Information .............32 Worldwide Sales and Design Support ..............32 Products ...........................................................32 PSoC Solutions ................................................32 CY8C9520A Page [+] Feedback ...

Page 3

... Each GPIO pin can be used to monitor and control various board level devices, including LEDs and system intrusion detection devices. The on board EEPROM can be used to store information such as error codes or board manufacturing data for read-back by application software for diagnostic purposes. CY8C9520A CY8C9540A, CY8C9560A GPortx 7 Drive Mode Registers Output ...

Page 4

... C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, ‘01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or ‘0x’ are decimal. CY8C9520A CY8C9540A, CY8C9560A on page 10, which illustrates memory reading Table 7 on page 11. ...

Page 5

... Port 1, Bit 2, PWM 2. 26 GPort1_Bit1_PWM0 Port 1, Bit 1, PWM 0. 27 GPort1_Bit0_PWM2 Port 1, Bit 0, PWM Supply voltage. dd Document Number: 38-12036 Rev. *E Figure 2. CY8C9520A 28-Pin Device Description GPort0_Bit0_PWM3 GPort0_Bit1_PWM1 GPort0_Bit2_PWM3 GPort0_Bit3_PWM1 GPort0_Bit4_PWM3 GPort0_Bit5_PWM1 GPort0_Bit6_PWM3 GPort0_Bit7_PWM1 I2C Serial Clock (SCL) I2C Serial Data (SDA) GPort2_Bit3_PWM3/A1 2 Write Disable ...

Page 6

... GPort0_Bit1_PWM5 GPort0_Bit2_PWM3 GPort0_Bit3_PWM1 GPort0_Bit4_PWM7 GPort0_Bit5_PWM5 GPort0_Bit6_PWM3 GPort0_Bit7_PWM1 GPort3_Bit0_PWM7 GPort3_Bit1_PWM5 GPort3_Bit2_PWM3 GPort3_Bit3_PWM1 GPort3_Bit4_PWM7 GPort3_Bit5_PWM5 GPort3_Bit6_PWM3 GPort3_Bit7_PWM1 GPort5_Bit2_PWM3 GPort5_Bit3_PWM1 I2C Serial Clock (SCL) I2C Serial Data (SDA) GPort2_Bit3_PWM3/A1 2 Write Disable. CY8C9520A CY8C9540A, CY8C9560A 48 1 Vdd 47 2 GPort1_Bit0_PWM6 46 GPort1_Bit1_PWM4 3 45 GPort1_Bit2_PWM2 GPort1_Bit3_PWM0 43 6 GPort1_Bit4_PWM6 42 7 ...

Page 7

... GPort0_Bit0_PWM7 96 DNU 97 GPort0_Bit1_PWM5 98 DNU 99 GPort0_Bit2_PWM3 100 DNU CY8C9520A CY8C9540A, CY8C9560A Description DNU = Do Not Use; leave floating. Port 5, Bit 1, PWM 8. Port 5, Bit 0, PWM 10. Port 5, Bit 4, PWM 12. Port 5, Bit 5, PWM 14. Port 4, Bit 7, PWM 8. Port 4, Bit 6, PWM 10. Port 4, Bit 5, PWM 12. Port 4, Bit 4, PWM 14. ...

Page 8

... GPort3_Bit7_PWM9 19 GPort5_Bit7_PWM15 20 GPort5_Bit6_PWM13 21 GPort5_Bit2_PWM11 22 GPort5_Bit3_PWM9 23 I2C Serial Clock (SCL) 24 DNU 25 Note 2. DNU = Do Not Use; leave floating. Document Number: 38-12036 Rev. *E [2] Figure 4. CY8C9560A 100-Pin Device TQFP CY8C9520A CY8C9540A, CY8C9560A DNU 75 74 GPort1_Bit3_PWM0 DNU 73 72 GPort1_Bit4_PWM6 71 DNU 70 GPort1_Bit5_PWM4/A6 69 GPort1_Bit6_PWM2/A5 GPort1_Bit7_PWM0/ GPort4_Bit0_PWM6 GPort4_Bit1_PWM4 ...

Page 9

... POR. When the part is held in reset, all In and Out pins are held at their default High-Z State. Document Number: 38-12036 Rev. *E Working with PWMs There are four independent PWMs in the CY8C9520A, eight in the CY8C9540A and sixteen in the CY8C9560A. Each I/O pin 2 C address. This can be configured as a PWM output by writing ‘ ...

Page 10

... Reading from GPort 1 Output to GPort 2 At this moment, device performs output to GPort data from GPort1 A data from GPort 2 ACK from ACK from Slave Writing from GPort 1 CY8C9520A CY8C9540A, CY8C9560A Stop data(Addr) A data(Addr+1) A ... N P ACK from ACK from No ACK Master Master from Master Stop ...

Page 11

... Output register data also affects pin states when PWMs are 00h enabled. See 00h See Figure 7 on page 10 illustrates port read/write procedures. FFh The Inversion registers have no effect on these ports. CY8C9520A CY8C9540A, CY8C9560A Default Register Register Value Select PWM for Port Output 00h Inversion 00h Pin Direction - Input/Output ...

Page 12

... Strong Drive Current PWM 22h Slow Strong Drive 23h High Impedance PWM Select Register (28h) This register is configures the PWM. Write a value of 00h-0Fh to this register to select the PWM to program with registers 29h-2Bh. CY8C9520A CY8C9540A, CY8C9560A Table 9. These registers Invert Input ...

Page 13

... corrupted then factory defaults are loaded and the low nibble of this register is set high to inform which set is active. The high nibble is always equal to 2 for CY8C9520A, 4 for CY8C9540A, and 6 for CY8C9560A. This register is read-only. Table 14. Device ID Status Register ...

Page 14

... Drive Modes Port 7 60h Config setting PWM0 61h Period setting PWM0 62h Pulse Width setting PWM0 63h – 65h PWM1 settings … … 8Dh – 8Fh PWM15 settings 90h Divider 91h Enable 92h CRC CY8C9520A CY8C9540A, CY8C9560A Table 16. Value Page [+] Feedback ...

Page 15

... Read 146 data bytes (see ■ Read 1 CRC byte. Reconfigure Device Cmd (07h) This command immediately reconfigures the device with actual POR defaults from EEPROM. It has the same effect on the registers as a POR. Table 16. CY8C9520A CY8C9540A, CY8C9560A Table 16). Page [+] Feedback ...

Page 16

... Typ Max Units °C -40 – +85 °C -40 – +100 CY8C9520A Unit of Measure Notes Higher storage temperatures reduces data retention time. Recommended storage temper- ature is +25°C ± 25°C. Extended duration storage temperatures above 65°C degrades reliability. Human Body Model ESD. Notes The temperature rise from ambient to junction is package specific ...

Page 17

... DC Chip-Level Specifications Table 20 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ guidance only. Table 20. CY8C9520A DC Chip-Level Specifications Symbol Description Vdd Supply voltage I Supply current Vdd 5V ...

Page 18

... OL note for V OL – 0.8 V Vdd = 3.0 to 5.5. – – V Vdd = 3.0 to 5.5. Gross tested to 1 μA. 1 – Package and pin dependent. Temp = 25°C. 3 Package and pin dependent. Temp = 25°C. CY8C9520A CY8C9540A, CY8C9560A Notes for GPort1; GPort2_Bit0 Page [+] Feedback ...

Page 19

... Min Typ Max – 0.1 – 2.5 23 1.46 1.5 1.53 91.40 93.75 96.09 CY8C9520A CY8C9540A, CY8C9560A Units Notes 12 MHz Normal Strong Mode 18 ns Vdd = 4.75 to 5.25V, 10 Vdd = 4.75 to 5.25V, 10% - 90% – ns Vdd = 3 to 5.25V, 10% - 90% – ns Vdd = 3 to 5.25V, 10% - 90% ...

Page 20

... SUSTAI2C T HDDATI2C Sr Repeated START Condition ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design A Min Typ – – – – CY8C9520A CY8C9540A, CY8C9560A Units Notes Max – kHz μs – μs – μs – μs – ...

Page 21

... Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation tools’ dimensions, refer to the emulator pod drawings at http://www.cypress.com. Document Number: 38-12036 Rev. *E Figure 10. 28-Pin (210-Mil) SSOP CY8C9520A CY8C9540A, CY8C9560A 51-85079 *D Page ...

Page 22

... Figure 11. 48-Pin (300-Mil) SSOP .020 1 0.395 0.420 0.292 0.299 48 SEATING PLANE 0.095 0.110 GAUGE PLANE 0.004 0.008 0.008 0.016 0.0135 Figure 12. 100-Pin ( 1.0 mm) TQFP CY8C9520A CY8C9540A, CY8C9560A DIMENSIONS IN INCHES MIN. MAX. 0.005 .010 0.010 0.024 0.040 0°-8° 51-85061 *D 51-85048 *D Page [+] Feedback ...

Page 23

... Table 31. Solder Reflow Peak Temperature Package 28 SSOP 48 SSOP 100 TQFP Notes + POWER x θ JA. Document Number: 38-12036 Rev. *E Maximum Peak Temperature Time at Maximum Peak Temperature 260 °C 260 °C 260 °C CY8C9520A CY8C9540A, CY8C9560A Typical θ [5] JA 101 °C/W 69 °C/W 48 °C Page [+] Feedback ...

Page 24

... Table 32 lists the CY8C95xxA device’s key package features and ordering codes. A definition of the ordering number code follows. Table 32. CY8C95xxA Device Key Features and Ordering Information Package 28 Pin (210 Mil) SSOP 28 Pin (210 Mil) SSOP (Tape and Reel) CY8C9520A-24PVXIT 48 Pin (300 Mil) SSOP 48 Pin (300 Mil) SSOP (Tape and Reel) CY8C9540A-24PVXIT 100 Pin TQFP ...

Page 25

... SSOP shrink small-outline package TQFP thin quad flat pack UART universal asynchronous reciever / transmitter USB universal serial bus WDT watchdog timer XRES external reset Symbol Unit of Measure nA nanoampere µs microsecond ms millisecond ns nanosecond V volts W watt mm millimeter % percent CY8C9520A Page [+] Feedback ...

Page 26

... The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to synchronize different logic blocks. comparator An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. Document Number: 38-12036 Rev. *E CY8C9520A CY8C9540A, CY8C9560A Page [+] Feedback ...

Page 27

... I2C uses only two bi-directional pins, clock and data, both running at +5V and pulled high with resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode. Document Number: 38-12036 Rev. *E CY8C9520A CY8C9540A, CY8C9560A Page [+] Feedback ...

Page 28

... Pinouts involve pin numbers as a link between schematic and PCB design (both being computer generated files) and may also involve pin names. Document Number: 38-12036 Rev. *E CY8C9520A CY8C9540A, CY8C9560A Page [+] Feedback ...

Page 29

... A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal system whose operation is synchronized by a clock signal. Document Number: 38-12036 Rev. *E CY8C9540A, CY8C9560A ® registered trademark and Programmable System-on- CY8C9520A Page [+] Feedback ...

Page 30

... A name for a power net meaning "voltage drain." The most positive power supply signal. Usually 3 name for a power net meaning "voltage source." The most negative power supply signal. SS watchdog timer A timer that must be serviced periodically not serviced, the CPU resets after a specified period of time. Document Number: 38-12036 Rev. *E CY8C9520A CY8C9540A, CY8C9560A Page [+] Feedback ...

Page 31

... Document History Page Document Title: CY8C9520A, CY8C9540A, CY8C9560A, 20, 40, and 60 Bit I/O Expander with EEPROM Document Number: 38-12036 Orig. of Submission Revision ECN No. Change ** 346754 HMT See ECN *A 392484 HMT See ECN *B 1336984 HMT/AESA See ECN *C 2843174 YARA 01/08/2010 *D 2903402 NJF 04/01/2010 ...

Page 32

... C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised December 14, 2010 2 C Patent Rights to use these components CY8C9520A CY8C9540A, CY8C9560A PSoC Solutions psoc.cypress.com/solutions PSoC 1 | ...

Related keywords