TP3410J National Semiconductor, TP3410J Datasheet - Page 9

• Manufacturer Part Number: TP3410J
• Manufacturer: National Semiconductor

Specifications of TP3410J

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

Functional Description
Format 2 Format 2 is the IDL in which the 2B
Format 3 This format provides time-slot assignment capa-
FSa defines B1 channel for Tx
FSb defines B1 channel for Rx
Delayed timing mode must be selected
Time-slot immediate mode only (no TSA)
ure 3-2 shows this format in DSI Slave Mode and
Figure 3-5 shows DSI Master Mode
transfer is assigned to the first 19 bits of the
frame on the Bx and Br pins Channels are as-
signed as follows B1 (8 bits) D (1 bit) 1 bit ig-
nored B2 (8 bits) D (1 bit) with the remaining
bits ignored until the next frame sync pulse Fig-
bility for the B1 and B2 channels which can be
independently assigned to any 8-bit wide time-
slot from 64 (or less) on the Bx and Br pins the
Transmit and Receive directions are also inde-
pendently assignable Also the D channel can be
assigned to any 2-bit wide time-slot from 256 (or
less) on the Bx and Br pins (D port disabled) or
(Continued)
FIGURE 3-2 DSI Format 2 (IDL) Slave Mode
FIGURE 3-1 DSI Format 1 Slave Mode
a
D data
9
Format 4 This is similar to the GCI format for the 2B
on the Dx and Dr pins (see D-Channel Port sec-
tion) Figure 3-3 shows this format in DSI Slave
Mode and Figure 3-6 shows DSI Master Mode
see also Section 6 2
channels but excludes the Monitor channel and
C I channel Channels are assigned to the first
26 bits of each frame as follows B1 (8 bits) B2
(8 bits) ignored (8 bits) D (2 bits) The remaining
bits in the frame are ignored until the next frame
sync pulse The relationship between BCLK and
data is the same as in the GCI mode for GCI
Channel 0 see Figure 7 (in DSI Master Mode
BCLK
put)
e
512 kHz and FS
a
is a square wave out-
TL H 9151– 5
TL H 9151– 6
a
D