TP3410J National Semiconductor, TP3410J Datasheet - Page 4

• Manufacturer Part Number: TP3410J
• Manufacturer: National Semiconductor

Specifications of TP3410J

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

Pin Descriptions
No
Pin
13
11
6
Symbol
Bx
Br
FSa
The digital input for multiplexed B D and
control data clocked by BCLK at the rate
of 1 data bit per 2 BCLK cycles and 32
data bits per 8 kHz frame defined by FSa
The open-drain n-channel output for multi-
plexed B D and control data clocked by
BCLK at the rate of 1 data bit per 2 BCLK
cycles and 32 data bits per 8 kHz frame
defined by FSa A pull-up resistor is re-
quired to define the logical 1 state
In GCI Slave mode (MO connected low)
this pin is the 8 kHz Frame Sync pulse in-
put requiring a positive edge to indicate
the start of the GCI slot time for both
transmit and receive data at Bx and Br In
GCI Master mode this pin is the 8 kHz
Frame Sync CMOS output pulse
(Continued)
Description
4
No
Pin
17 S2 CLS
19 S1
18 ES1
16 ES2
15 LEC
7
SO FSb
Symbol
In GCI Slave mode (MO
input pins S2 S1 and S0 together pro-
vide a 3-bit binary-coded select port for
the GCI channel number S2 is the msb
These pins must be connected either to
V
slots which are available if BCLK
MHz is used
In GCI Master mode (MO
S2 CLS is the GCI Clock Select input
Connect this pin high to select BCLK
1 536 MHz connect CLS low to select
BCLK
Sync CMOS output pulse which identifies
the B2 channel
While in GCI mode the ES1 ES2 pins are
local input pins The status of the pins can
be accessed via the RXM56 register bits
5 6 corresponding to ES1 ES2
Latched External Control output which is
the output of a latched bit in the TXM56
Register
CC
D or GND to select the 1-of-8 GCI
e
512 kHz SO FSb is a Frame
Description
e
e
0)
1)
t
4 096
e