TP3410J National Semiconductor, TP3410J Datasheet - Page 3

• Manufacturer Part Number: TP3410J
• Manufacturer: National Semiconductor

Specifications of TP3410J

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

Pin Descriptions
PIN DESCRIPTIONS SPECIFIC TO MICROWIRE MODE
ONLY (MW
No
Load with 33 pF to GND each side (
Pin
28
12
13
11
18
19
Crystal specifications 15 36 MHz
2
3
6
7
Symbol
Li
Li
MW
BCLK
FSa
FSb
Bx
Br
CI
CO
a
b
e
1)
Receive 2B1Q signal differential inputs
from the line transformer For normal full-
duplex operation these pins should be
connected to the Lo
recommended coupling circuit as shown
in the Applications section
The Microwire GCI Select pin which must
be tied to V
Interface with any of the data formats at
the Digital System Interface
The Bit Clock pin which determines the
data shift rate for ‘B’ and ‘D’ channel data
on the digital interface side of the device
When Digital System Interface (DSI) Slave
mode is selected (see Digital Interfaces
section) BCLK is an input which may be
any multiple of 8 kHz from 256 kHz to
4 096 MHz It need not be synchronous
with MCLK
When DSI Master mode is selected this
pin is a CMOS output clock at 256 kHz
512 kHz 1 536 MHz 2 048 MHz or 2 56
MHz depending on the selection in Com-
mand Register 1 It is synchronous with
the data on Bx and Br
In DSI Slave mode this pin is the Transmit
Frame Sync pulse input requiring a posi-
tive edge to indicate the start of the active
channel time for transmit B1 channel data
into Bx In DSI Master mode this pin is a
Frame Sync CMOS output pulse conform-
ing with the selected Digital Interface for-
mat
In DSI Slave mode this pin is the Receive
Frame Sync pulse input requiring a posi-
tive edge to indicate the start of the active
channel time of the device for receive B
channel data out from Br (see DSI Format
section) In DSI Master mode this pin is a
Frame Sync CMOS output pulse conform-
ing with the selected Digital Interface for-
mat
The digital input for B and if selected D
channel data to be transmitted to the line
must be synchronous with BCLK
The TRI-STATE output for B and if select-
ed D channel data received from the line
it is synchronous with BCLK
The Microwire control channel data input
The Microwire control channel TRI-STATE
output for status information When not
enabled by CS this output is high-imped-
ance
g
(Continued)
a
50 ppm parallel resonant R
CC
7 pF due to pin capacitance)
Description
D to enable the Microwire
g
pins through the
S s
20
3
No
PIN DESCRIPTIONS SPECIFIC TO GCI MODE ONLY
(MW
No
Pin
Pin
17
27
26
16
15
14
28
27
12
e
Symbol
CCLK
CS
INT
Dx
Dr
DCLK
Symbol
MW
MO
BCLK
0)
The Microwire control channel Clock input
which may be asynchronous with BCLK
The Chip Select input which enables the
Control channel data to be shifted in and
out when pulled low When high this pin
inhibits the Control interface
The Interrupt output a latched open-drain
output signal which is normally high-im-
pedance and goes low to indicate a
change of status of the loop transmission
system This latch is cleared when the
Status Register is read by the microproc-
essor
When the D-port is enabled this pin is the
digital input for D channel data to be trans-
mitted to the line clocked by DCLK or
BCLK see Register CR2 When the D-port
is disabled via CR2 this pin must be tied to
GND
When the D-port is enabled this pin is the
TRI-STATE output for D channel data to
be received from the line clocked by DCLK
or BCLK see Register CR2
When the D-port is enabled in DSI Slave
or Master mode this is a 16 kHz clock
CMOS output for D channel data When
the D-port is disabled or not used this pin
must be left open-circuit
The Microwire GCI select input which
must be tied to GND to enable the GCI
mode at the Digital System Interface
The GCI Master Slave select input for the
clock direction Connect this pin low to se-
lect BCLK and FSa as inputs i e
Slave Selection of LT or NT mode must
be made in register CR2 When MO is con-
nected high NT Mode is automatically se-
lected and BCLK FSa and FSb are out-
puts i e the GCI Master see Section 8
The Bit Clock pin which controls the shift-
ing of data on the Bx and Br pins at a rate
of 2 BCLK cycles per data bit When GCI
Slave mode is selected (see Digital Inter-
faces section) BCLK is an input which
may be any multiple of 16 kHz from
512 kHz to 6 144 MHz It need not be syn-
chronous with MCLK
When GCI Master mode is selected this
pin is a CMOS output clock at 512 kHz or
1 536 MHz depending on the connection
of the S2 CLS pin It is synchronous with
the data on Bx and Br
Description
Description
GCI