TP3410J National Semiconductor, TP3410J Datasheet - Page 6

• Manufacturer Part Number: TP3410J
• Manufacturer: National Semiconductor

Specifications of TP3410J

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

Superframe
Superframe
Functional Description
Note 8
bits other than the Sync Word are scrambled
Symbols
act
aib
crc
cso
dea
eoc
febe
2 3
2 3
1
1
c
1 5 ms Basic Frames
e
e
e
e
e
e
e
Abbreviations
start-up bit (
alarm indication bit (
tion)
cyclic redundacy check covers 2B
1
2
cold-start-only bit (
only)
turn off bit (
embedded operations channel
a
dm
i
far end block error bit (
frame)
e
e
e
e
e
Quat Positions
Quat Positions
Basic Frame
Basic Frame
most significant bit
next significant bit etc
address bits
data message indicator (0
1
information (data or message)
Bit Positions
Bit Positions
e
message)
e
e
1
2
3
4
5
6
7
8
1
1
2
3
4
5
6
7
8
1
e
0 to announce turn off)
1 during start-up)
TABLE I 2B1Q Superframe Format and Overhead Bit Assignments
12 ms Superframe NT-to-Network superframe is offset from Network-to-NT superframe by 60
e
e
1 to indicate cold-start-
e
0 to indicate interrup-
Sync Word
Sync Word
(Continued)
Framing
Framing
0 for errored super-
1–18
1–18
1–9
ISW
ISW
ISW
ISW
1–9
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
a
D
e
a
(b) NT
(a) Network
12x(2B
12x(2B
data
M
10– 117
19–234
10–117
19– 234
2B
2B
2B
2B
2B
2B
2B
2B
2B
2B
2B
2B
2B
2B
2B
2B
2B
2B
4
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
6
D)
D)
Network
ntm
ps1 ps2
Quat
sai
uoa
‘‘1’’
‘‘1 ’’
2B
M
SW ISW
a
eocd
eocd
eoc
eoc
eoca
eoca
eoca
eoca
NT
eoci
eoci
eoci
eoci
eoci
eoci
eoci
eoci
118s
118s
235
235
M
M
D
1
1
dm
dm
m
3
6
m
3
6
3
6
3
6
1
1
1
1
e
e
e
e
e
e
e
e
e
e
NT in test mode bit (
power status bits (
lems)
pair of bits forming quaternary symbol
s
m
S-activation-indication bit (
U-only-activation bit (
reserved bit for future standard (
network indicator bit (
use)
user data bits 19– 234 in frame
M-channel bits 235– 240 in frame
synchronization word inverted synchronization
word bits 1– 18 in frame
eoca
eoca
eoca
eoca
118m
118m
eoci
eoci
eoci
eoci
eoci
eoci
eoci
eoci
eoci
eoci
eoci
eoci
236
236
M
M
e
e
2
2
1
4
7
1
4
7
1
4
7
1
4
7
2
2
2
2
sign bit (first in quat)
magnitude bit (second in quat)
Overhead Bits (M
Overhead Bits (M
eoca
eoca
eoca
eoca
eoci
eoci
eoci
eoci
eoci
eoci
eoci
eoci
eoci
eoci
eoci
eoci
119s
119s
237
237
M
M
3
3
2
5
8
2
5
8
2
5
8
2
5
8
3
3
3
3
e
e
e
e
0 to indicate power prob-
119m
119m
238
dea
uoa
238
ntm
0 to indicate test mode)
ps
ps
cso
g
act
M
act
M
aib
1 reserved for network
1 to activate S T)
1
1
1
1
1
1
1
2 quats (about 0 75 ms) All
1
1
4
4
1
2
–M
–M
e
1 for S T activity)
6
6
)
)
crc
crc
120s
120s
e
crc
crc
crc
crc
crc
crc
crc
crc
crc
crc
239
239
M
M
1
1
1
1
5
5
11
11
1)
1
3
5
7
9
1
3
5
7
9
120m
120m
crc
crc
crc
crc
febe
febe
crc
crc
crc
crc
crc
crc
crc
crc
240
240
M
M
1
1
6
10
12
6
10
12
2
4
6
8
2
4
6
8