PIC18F4620-I/P Microchip Technology Inc., PIC18F4620-I/P Datasheet - Page 35

• Manufacturer Part Number: PIC18F4620-I/P
• Description: 40 Pin, 64 KB Flash, 3968 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4620-I/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 36
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 64K Bytes
• Ram Size: 4K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 3-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

3.0
PIC18F2525/2620/4525/4620 devices offer a total of
seven operating modes for more efficient power
management. These modes provide a variety of
options for selective power conservation in applications
where resources may be limited (i.e., battery-powered
devices).
There are three categories of power managed modes:
• Run modes
• Idle modes
• Sleep mode
These categories define which portions of the device
are clocked and sometimes, what speed. The Run and
Idle modes may use any of the three available clock
sources (primary, secondary or internal oscillator
block); the Sleep mode does not use a clock source.
The power managed modes include several power-
saving features offered on previous PICmicro
devices. One is the clock switching feature, offered in
other PIC18 devices, allowing the controller to use the
Timer1 oscillator in place of the primary oscillator. Also
included is the Sleep mode, offered by all PICmicro
devices, where all device clocks are stopped.
3.1
Selecting a power managed mode requires two
decisions: if the CPU is to be clocked or not and the
selection
(OSCCON<7>) controls CPU clocking, while the
SCS1:SCS0 bits (OSCCON<1:0>) select the clock
source. The individual modes, bit settings, clock sources
and affected modules are summarized in Table 3-1.
TABLE 3-1:
 2004 Microchip Technology Inc.
Sleep
PRI_RUN
SEC_RUN
RC_RUN
PRI_IDLE
SEC_IDLE
RC_IDLE
Note 1:
Mode
2:
POWER MANAGED MODES
Selecting Power Managed Modes
of
IDLEN reflects its value when the SLEEP instruction is executed.
Includes INTOSC and INTOSC postscaler, as well as the INTRC source.
IDLEN
a
<7>
N/A
N/A
N/A
POWER MANAGED MODES
0
1
1
1
clock
OSCCON Bits
(1)
SCS1:SCS0
source.
<1:0>
N/A
00
01
1x
00
01
1x
The
Clocked
Clocked
Clocked
IDLEN
CPU
Module Clocking
PIC18F2525/2620/4525/4620
Off
Off
Off
Off
bit
®
Peripherals
Clocked
Clocked
Clocked
Clocked
Clocked
Clocked
Off
3.1.1
The SCS1:SCS0 bits allow the selection of one of three
clock sources for power managed modes. They are:
• the primary clock, as defined by the
• the secondary clock (the Timer1 oscillator)
• the internal oscillator block (for RC modes)
3.1.2
Switching from one power managed mode to another
begins by loading the OSCCON register. The
SCS1:SCS0 bits select the clock source and determine
which Run or Idle mode is to be used. Changing these
bits causes an immediate switch to the new clock
source, assuming that it is running. The switch may
also be subject to clock transition delays. These are
discussed in Section 3.1.3 “Clock Transitions and
Status Indicators” and subsequent sections.
Entry to the Power Managed Idle or Sleep modes is
triggered by the execution of a SLEEP instruction. The
actual mode that results depends on the status of the
IDLEN bit.
Depending on the current mode and the mode being
switched to, a change to a power managed mode does
not always require setting all of these bits. Many
transitions may be done by changing the oscillator select
bits, or changing the IDLEN bit, prior to issuing a SLEEP
instruction. If the IDLEN bit is already configured
correctly, it may only be necessary to perform a SLEEP
instruction to switch to the desired mode.
FOSC3:FOSC0 configuration bits
None – All clocks are disabled
Primary – LP, XT, HS, HSPLL, RC, EC and
Internal Oscillator Block
This is the normal full power execution mode.
Secondary – Timer1 Oscillator
Internal Oscillator Block
Primary – LP, XT, HS, HSPLL, RC, EC
Secondary – Timer1 Oscillator
Internal Oscillator Block
Available Clock and Oscillator Source
CLOCK SOURCES
ENTERING POWER MANAGED
MODES
(2)
(2)
(2)
.
DS39626B-page 33