PIC18F4620-I/P Microchip Technology Inc., PIC18F4620-I/P Datasheet - Page 173

• Manufacturer Part Number: PIC18F4620-I/P
• Description: 40 Pin, 64 KB Flash, 3968 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4620-I/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 36
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 64K Bytes
• Ram Size: 4K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 3-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

REGISTER 17-3:
 2004 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SSPSTAT: MSSP STATUS REGISTER (I
bit 7
SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for High-Speed mode (400 kHz)
CKE: SMBus Select bit
In Master or Slave mode:
1 = Enable SMBus specific inputs
0 = Disable SMBus specific inputs
D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
S: Start bit
1 = Indicates that a Start bit has been detected last
0 = Start bit was not detected last
R/W: Read/Write Information bit (I
In Slave mode:
1 = Read
0 = Write
In Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
UA: Update Address bit (10-bit Slave mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
BF: Buffer Full Status bit
In Transmit mode:
1 = SSPBUF is full
0 = SSPBUF is empty
In Receive mode:
1 = SSPBUF is full (does not include the ACK and Stop bits)
0 = SSPBUF is empty (does not include the ACK and Stop bits)
Legend:
R = Readable bit
-n = Value at POR
R/W-0
Note:
Note:
Note:
Note:
SMP
This bit is cleared on Reset and when SSPEN is cleared.
This bit is cleared on Reset and when SSPEN is cleared.
This bit holds the R/W bit information following the last address match. This bit is
only valid from the address match to the next Start bit, Stop bit or not ACK bit.
ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is
in Active mode.
R/W-0
CKE
PIC18F2525/2620/4525/4620
W = Writable bit
‘1’ = Bit is set
D/A
R-0
Preliminary
2
C mode only)
R-0
P
2
C MODE)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R-0
S
R/W
R-0
x = Bit is unknown
R-0
UA
DS39626B-page 171
R-0
BF
bit 0