PIC18F4620-I/P Microchip Technology Inc., PIC18F4620-I/P Datasheet - Page 234

• Manufacturer Part Number: PIC18F4620-I/P
• Description: 40 Pin, 64 KB Flash, 3968 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4620-I/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 36
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 64K Bytes
• Ram Size: 4K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 3-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2525/2620/4525/4620
19.8
An A/D conversion can be started by the Special Event
Trigger of the CCP2 module. This requires that the
CCP2M3:CCP2M0
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conversion and the Timer1 (or Timer3) counter will
be reset to zero. Timer1 (or Timer3) is reset to automat-
ically repeat the A/D acquisition period with minimal
software overhead (moving ADRESH:ADRESL to the
TABLE 19-2:
DS39626B-page 232
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
PORTA
TRISA
PORTB
TRISB
LATB
PORTE
TRISE
LATE
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1:
Name
(4)
2:
3:
4:
(4)
(4)
Use of the CCP2 Trigger
These bits are unimplemented on 28-pin devices; always maintain these bits clear.
PORTA<7:6> and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
RE3 port bit is available only as an input pin when the MCLRE configuration bit is ‘0’.
These registers are not implemented on 28-pin devices.
PORTB Data Direction Control Register
PORTB Data Latch Register (Read and Write to Data Latch)
A/D Result Register High Byte
TRISA7
GIE/GIEH PEIE/GIEL TMR0IE
A/D Result Register Low Byte
PSPIF
PSPIE
PSPIP
OSCFIE
OSCFIP
OSCFIF
RA7
ADFM
Bit 7
RB7
IBF
—
—
—
—
REGISTERS ASSOCIATED WITH A/D OPERATION
(1)
(1)
(1)
(1)
(2)
bits
TRISA6
RA6
CMIF
CMIE
CMIP
ADIE
ADIP
ADIF
Bit 6
OBF
RB6
—
—
—
—
—
(CCP2CON<3:0>)
(1)
(2)
PORTA Data Direction Control Register
VCFG1
ACQT2
CHS3
RCIE
RCIP
IBOV
RCIF
Bit 5
RA5
RB5
—
—
—
—
—
PSPMODE
VCFG0
ACQT1
INT0IE
Preliminary
CHS2
TXIE
TXIP
EEIF
EEIE
EEIP
Bit 4
TXIF
be
RA4
RB4
—
—
PCFG3
ACQT0
SSPIE
SSPIP
SSPIF
BCLIF
BCLIE
BCLIP
RE3
CHS1
desired location). The appropriate analog input
channel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate
T
sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D
module but will still reset the Timer1 (or Timer3)
counter.
RBIE
Bit 3
RA3
RB3
ACQ
—
—
(3)
time selected before the Special Event Trigger
PORTE Data Latch Register
TMR0IF
CCP1IF
CCP1IE
CCP1IP
HLVDIF
HLVDIE
HLVDIP
TRISE2
PCFG2
ADCS2
CHS0
Bit 2
RA2
RB2
RE2
GO/DONE
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
TRISE1
PCFG1
ADCS1
INT0IF
Bit 1
 2004 Microchip Technology Inc.
RA1
RB1
RE1
TMR1IF
TMR1IE
TMR1IP
CCP2IE
CCP2IP
CCP2IF
TRISE0
PCFG0
ADCS0
ADON
RBIF
Bit 0
RA0
RB0
RE0
on page
Values
Reset
49
52
52
52
52
52
52
51
51
51
51
51
52
52
52
52
52
52
52
52