PIC18F4620-I/P Microchip Technology Inc., PIC18F4620-I/P Datasheet - Page 148

• Manufacturer Part Number: PIC18F4620-I/P
• Description: 40 Pin, 64 KB Flash, 3968 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4620-I/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 36
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 64K Bytes
• Ram Size: 4K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 3-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2525/2620/4525/4620
TABLE 15-5:
DS39626B-page 146
INTCON
RCON
PIR1
PIE1
IPR1
TRISB
TRISC
TMR2
PR2
T2CON
CCPR1L
CCPR1H
CCP1CON
CCPR2L
CCPR2H
CCP2CON
ECCP1AS
PWM1CON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2.
Note 1:
Name
2:
The SBOREN bit is only available when the BOREN1:BOREN0 configuration bits = 01; otherwise, it is
disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”.
These bits are unimplemented on 28-pin devices and read as ‘0’.
PORTB Data Direction Control Register
PORTC Data Direction Control Register
Timer2 Register
Timer2 Period Register
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 1 High Byte
Capture/Compare/PWM Register 2 Low Byte
Capture/Compare/PWM Register 2 High Byte
ECCPASE ECCPAS2
GIE/GIEH PEIE/GIEL
PSPIF
PSPIE
PSPIP
P1M1
PRSEN
IPEN
Bit 7
—
—
REGISTERS ASSOCIATED WITH PWM AND TIMER2
(2)
(2)
(2)
(2)
SBOREN
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
P1M0
PDC6
ADIF
ADIE
ADIP
Bit 6
—
(2)
(2)
(1)
ECCPAS1 ECCPAS0
TMR0IE
PDC5
DC1B1
DC2B1
RCIE
RCIP
RCIF
Bit 5
—
(2)
Preliminary
PDC4
DC1B0
DC2B0
INT0IE
TXIE
TXIP
Bit 4
TXIF
RI
(2)
CCP1M3
CCP2M3
PSSAC1
PDC3
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
TO
(2)
CCP1M2
CCP2M2
PSSAC0 PSSBD1
TMR0IF
CCP1IE
CCP1IP
PDC2
CCP1IF
Bit 2
PD
(2)
CCP1M1
CCP2M1
TMR2IE
TMR2IP
PDC1
 2004 Microchip Technology Inc.
TMR2IF
INT0IF
Bit 1
POR
(2)
(2)
PSSBD0
CCP1M0
CCP2M0
TMR1IF
TMR1IE
TMR1IP
PDC0
RBIF
Bit 0
BOR
(2)
(2)
on page
Values
Reset
49
48
52
52
52
52
52
50
50
50
51
51
51
51
51
51
51
51