DP83905AVQB National Semiconductor, DP83905AVQB Datasheet - Page 34

• Manufacturer Part Number: DP83905AVQB
• Description: IC CONTROLR AT/LAN TP IN 160PQFP
• Manufacturer: National Semiconductor
• Series: AT/LANTIC™r

Specifications of DP83905AVQB

• Controller Type: AT, LAN Twisted-Pair Interface Controller
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 100mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP83905AVQB

Bits
D0
D1
D2
D3
D4
D5
D6
D7
5 0 Register Descriptions
INTERRUPT STATUS REGISTER (ISR)
This register is accessed by the host processor to determine the cause of an interrupt Any interrupt can be masked in the
Interrupt Mask Register (IMR) Individual interrupt bits are cleared by writing a ‘‘1’’ into the corresponding bit of the ISR The
valid interrupt output is active as long as any unmasked signal is set and will not go low until all unmasked bits in this register
have been cleared The ISR must be cleared after power up by writing it with all 1’s
Symbols
PRX
PTX
RXE
TXE
OVW
CNT
RDC
RST
PACKET RECEIVED Indicates packet received with no errors
PACKET TRANSMITTED Indicates packet transmitted with no errors
RECEIVE ERROR Indicates that a packet was received with one or more of the following errors
TRANSMIT ERROR Set when packet transmitted with one or more of the following errors
OVERWRITE WARNING Set when receive buffer ring storage resources have been exhausted (Local
DMA has reached Boundary Pointer)
COUNTER OVERFLOW Set when MSB of one or more of the Network Tally Counters has been set
REMOTE DMA COMPLETE Set when Remote DMA operation has been completed
RESET STATUS Set when AT LANTIC Controller enters reset state and cleared when a Start
Command is issued to the CR This bit is also set when a Receive Buffer Ring overflow occurs and is
cleared when one or more packets have been removed from the ring Writing to this bit has no effect
Note This bit does not generate an interrupt it is merely a status indicator
CRC Error
Frame Alignment Error
FIFO Overrun
Missed Packet
Excessive Collisions
FIFO Underrun
RST
7
RDC
6
(Continued)
CNT
07H (READ WRITE)
5
OVW
4
34
Description
TXE
3
RXE
2
PTX
1
PRX
0