DP83905AVQB National Semiconductor, DP83905AVQB Datasheet - Page 18

• Manufacturer Part Number: DP83905AVQB
• Description: IC CONTROLR AT/LAN TP IN 160PQFP
• Manufacturer: National Semiconductor
• Series: AT/LANTIC™r

Specifications of DP83905AVQB

• Controller Type: AT, LAN Twisted-Pair Interface Controller
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 100mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP83905AVQB

4 0 Functional Description
For the case of a 4 word threshold using a 20 MHz BSCLK
To prevent a FIFO underrun a byte (or word) of data must
be added from the FIFO before the last byte is removed
Therefore the worst case tolerable latency is the time from
the effective threshold being reached to the time the last
byte is removed minus the time taken to load the first byte
(or word) of data to the FIFO during a local DMA burst (8
BSCLKs)
For the case of a 4 word threshold using a 20 MHz BSCLK
The worst case latency either overrun or underrun ulti-
mately limits the overall latency that the AT LANTIC Con-
troller can tolerate If the standard ISA cycles are shorter
than the worst case latency then no FIFO overruns or un-
derruns will occur
BEGINNING OF RECEIVE
At the beginning or reception the AT LANTIC Controller
stores entire Address field of each incoming packet in the
FIFO to determine whether the packet matches its Physical
Address Registers or maps to one of its Multicast Registers
This causes the FIFO to accumulate 8 bytes
Furthermore there are some synchronization delays in the
DMA PLA Thus the actual time that a request to access
the buffer RAM is asserted from the time the Start of Frame
Delimiter (SFD) is detected is 7 8 s This operation affects
the bus latencies at 2 byte and 4 byte thresholds during the
first receive request since the FIFO must be filled to 8 bytes
(or 4 words) before issuing a request to the buffer RAM
END OF RECEIVE
When the end of a packet is detected by the ENDEC mod-
ule the AT LANTIC Controller enters its end of packet pro-
cessing sequence emptying its FIFO and writing the status
information at the beginning of the packet The AT LANTIC
Controller holds onto the memory bus for the entire se-
quence The longest time that local DMA will hold the buffer
RAM occurs when a packet ends just as the AT LANTIC
Controller performs its last FIFO burst The AT LANTIC
Controller in this case performs a programmed burst trans-
fer followed by flushing the remaining bytes in the FIFO and
completed by writing the header information to the buffer
memory The following steps occur during this sequence
tolerable latency
tolerable latency
tolerable latency
c
b
time to transfer byte on network)
time to fill 1st FIFO location
e
e
e
e
e
((13
2 s
(4
2 8 s
(threshold
c
b
800)
10)
b
c
(8
800)
c
50) ns
b
(8
(Continued)
c
50) ns
18
1 AT LANTIC Controller issues request to access the
2 During the burst packet ends resulting in the request
3 AT LANTIC Controller flushes remaining bytes from
4 AT LANTIC Controller performs internal processing to
5 AT LANTIC Controller writes 4-byte (2-word) header
6 AT LANTIC Controller de-asserts access to the buffer
BEGINNING OF TRANSMIT
Before transmitting the AT LANTIC Controller performs a
prefetch from memory to load the FIFO The number of
bytes prefetched is the programmed FIFO threshold The
next request to the buffer RAM is not issued until after the
AT LANTIC Controller actually begins transmitting data i e
after SFD
READING THE FIFO
If the FIFO is read during normal operation the AT LANTIC
Controller will ‘‘hang’’ the ISA bus by deasserting CHRDY
and never asserting it The FIFO should only be read during
loopback diagnostics when it will operate normally
PROTOCOL PLA
The Protocol PLA is responsible for implementing the IEEE
802 3 protocol including collision recovery with random
backoff The Protocol PLA also formats packets during
transmission and strips preamble and synch during recep-
tion
DMA AND BUFFER CONTROL LOGIC
The DMA and Buffer Control Logic is used to control two
16-bit DMA channels During reception the Local DMA
stores packets in a receive buffer ring located in buffer
memory During transmission the Local DMA uses pro-
grammed pointer and length registers to transfer a packet
from local buffer memory to the FIFO
A second DMA channel is used when the AT LANTIC Con-
troller is used in I O Port mode This DMA is used as a slave
DMA to transfer data between the local buffer memory and
the host system The Local DMA and Remote DMA are in-
ternally arbitrated with the Local DMA channel having high-
est priority Both DMA channels use a common external bus
clock to generate all required bus timing External arbitration
is performed with a standard bus request bus acknowledge
handshake protocol
In the shared memory mode the Remote DMA is not used
because in this mode the system has direct read write ac-
cess to the buffer RAM
RAM because the FIFO threshold has been reached
being extended
FIFO
prepare for writing the header
RAM