CY7C67200-48BAXI Cypress Semiconductor Corp, CY7C67200-48BAXI Datasheet - Page 54

• Manufacturer Part Number: CY7C67200-48BAXI
• Description: USB HOST/PERIPH CNTRLR 48LFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-OTG™r
• Type: OTG Programmable USB On The Gor

Specifications of CY7C67200-48BAXI

• Package / Case: 48-LFBGA
• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 2.7 V ~ 3.6 V, 3 V ~ 3.6 V
• Current - Supply: 80mA, 135mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Operating Supply Voltage: 2.7 V to 3.6 V
• Controller Family/series: PSoC 1
• Core Size: 16 Bit
• No. Of I/o's: 25
• Program Memory Size: 16KB
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2262; CY7C67200-48BAXI

Document #: 38-08014 Rev. *G
3Wire Enable (Bit 15)
The 3Wire Enable bit indicates if the MISO and MOSI data
lines are tied together allowing only half duplex operation.
1: MISO and MOSI data lines are tied together
0: Normal MISO and MOSI Full Duplex operation (not tied
together)
Phase Select (Bit 14)
The Phase Select bit selects advanced or delayed SCK phase.
This field only applies to master mode.
1: Advanced SCK phase
0: Delayed SCK phase
SCK Polarity Select (Bit 13)
This SCK Polarity Select bit selects the polarity of SCK.
1: Positive SCK polarity
0: Negative SCK polarity
Scale Select (Bits [12:9])
The Scale Select field provides control over the SCK
frequency, based on 48 MHz. See
this field. This field only applies to master mode.
Table 34.Scale Select Field Definition for SCK Frequency
Scale Select [12:9]
0000
0001
0010
0100
0101
1000
1001
1010
0011
0110
0111
1011
1100
1101
1110
1111
Table 34
SCK Frequency
750 KHz
500 KHz
375 KHz
250 KHz
375 KHz
250 KHz
375 KHz
250 KHz
1.5 MHz
12 MHz
8 MHz
6 MHz
4 MHz
3 MHz
2 MHz
1 MHz
for a definition of
Master Active Enable (Bit 7)
The Master Active Enable bit is a read-only bit that indicates if
the master state machine is active or idle. This field only
applies to master mode.
1: Master state machine is active
0: Master state machine is idle
Master Enable (Bit 6)
The Master Enable bit sets the SPI interface to master or
slave. This bit is only writable when the Master Active Enable
bit reads ‘0’, otherwise value will not change.
1: Master SPI interface
0: Slave SPI interface
SS Enable (Bit 5)
The SS Enable bit enables or disables the master SS output.
1: Enable master SS output
0: Disable master SS output (three-state master SS output, for
single SS line in slave mode)
SS Delay Select (Bits [4:0])
When the SS Delay Select field is set to ‘00000’ this indicates
manual mode. In manual mode SS is controlled by the SS
Manual bit of the SPI Control register. When the SS Delay
Select field is set between ‘00001’ to ‘11111’, this value
indicates the count in half bit times of auto transfer delay for:
SS LOW to SCK active, SCK inactive to SS HIGH, SS HIGH
time. This field only applies to master mode.
CY7C67200
Page 54 of 78
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