CY7C67200-48BAXI Cypress Semiconductor Corp, CY7C67200-48BAXI Datasheet - Page 32

• Manufacturer Part Number: CY7C67200-48BAXI
• Description: USB HOST/PERIPH CNTRLR 48LFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-OTG™r
• Type: OTG Programmable USB On The Gor

Specifications of CY7C67200-48BAXI

• Package / Case: 48-LFBGA
• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 2.7 V ~ 3.6 V, 3 V ~ 3.6 V
• Current - Supply: 80mA, 135mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Operating Supply Voltage: 2.7 V to 3.6 V
• Controller Family/series: PSoC 1
• Core Size: 16 Bit
• No. Of I/o's: 25
• Program Memory Size: 16KB
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2262; CY7C67200-48BAXI

Document #: 38-08014 Rev. *G
IN Exception Flag (Bit 8)
The IN Exception Flag bit indicates when the device received
an IN packet when armed for an OUT.
1: Received IN when armed for OUT
0: Received OUT when armed for OUT
Stall Flag (Bit 7)
The Stall Flag bit indicates that a Stall packet was sent to the
host.
1: Stall packet was sent to the host
0: Stall packet was not sent
NAK Flag (Bit 6)
The NAK Flag bit indicates that a NAK packet was sent to the
host.
1: NAK packet was sent to the host
0: NAK packet was not sent
Length Exception Flag (Bit 5)
The Length Exception Flag bit indicates the received data in
the data stage of the last transaction does not equal the
maximum Endpoint Count specified in the Device n Endpoint
n Count register. A Length Exception can either mean an
overflow or underflow and the Overflow and Underflow flags
(bits 11 and 10, respectively) should be checked to determine
which event occurred.
1: An overflow or underflow condition occurred
0: An overflow or underflow condition did not occur
Setup Flag (Bit 4)
The Setup Flag bit indicates that a setup packet was received.
In device mode setup packets are stored at memory location
0x0300 for Device 1 and 0x0308 for Device 2. Setup packets
are always accepted regardless of the Direction Select and
Arm Enable bit settings as long as the Device n EP n Control
register Enable bit is set.
1: Setup packet was received
0: Setup packet was not received
Sequence Flag (Bit 3)
The Sequence Flag bit indicates whether the last data toggle
received was a DATA1 or a DATA0. This bit has no effect on
receiving data packets; sequence checking must be handled
in firmware.
1: DATA1 was received
0: DATA0 was received
Timeout Flag (Bit 2)
The Timeout Flag bit indicates whether a timeout condition
occurred on the last transaction. On the device side, a timeout
can occur if the device sends a data packet in response to an
IN request but then does not receive a handshake packet in a
predetermined time. It can also occur if the device does not
receive the data stage of an OUT transfer in time.
1: Timeout occurred
0: Timeout condition did not occur
Error Flag (Bit 2)
The Error Flag bit is set if a CRC5 and CRC16 error occurs, or
if an incorrect packet type is received. Overflow and Underflow
are not considered errors and do not affect this bit.
1: Error occurred
0: Error did not occur
ACK Flag (Bit 0)
The ACK Flag bit indicates whether the last transaction was
ACKed.
1: ACK occurred
0: ACK did not occur
CY7C67200
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