CY7C67200-48BAXI Cypress Semiconductor Corp, CY7C67200-48BAXI Datasheet - Page 19

• Manufacturer Part Number: CY7C67200-48BAXI
• Description: USB HOST/PERIPH CNTRLR 48LFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-OTG™r
• Type: OTG Programmable USB On The Gor

Specifications of CY7C67200-48BAXI

• Package / Case: 48-LFBGA
• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 2.7 V ~ 3.6 V, 3 V ~ 3.6 V
• Current - Supply: 80mA, 135mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Operating Supply Voltage: 2.7 V to 3.6 V
• Controller Family/series: PSoC 1
• Core Size: 16 Bit
• No. Of I/o's: 25
• Program Memory Size: 16KB
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2262; CY7C67200-48BAXI

Document #: 38-08014 Rev. *G
Port A D+ Status (Bit 13)
The Port A D+ Status bit is a read-only bit that indicates the
value of DATA+ on Port A.
1: D+ is high
0: D+ is low
Port A D– Status (Bit 12)
The Port A D– Status bit is a read-only bit that indicates the
value of DATA– on Port A.
1: D– is high
0: D– is low
LOA (Bit 10)
The LOA bit selects the speed of Port A.
1: Port A is set to Low-speed mode
0: Port A is set to Full-speed mode
Mode Select (Bit 9)
The Mode Select bit sets the SIE for host or device operation.
When set for device operation only one USB port is supported.
The active port is selected by the Port Select bit in the Host n
Count Register.
1: Host mode
0: Device mode
Port A Resistors Enable (Bit 7)
The Port A Resistors Enable bit enables or disables the
pull-up/pull-down resistors on Port A. When enabled, the
Mode Select bit and LOA bit of this register sets the
pull-up/pull-down resistors appropriately. When the Mode
Select is set for Host mode, the pull-down resistors on the data
lines (D+ and D–) are enabled. When the Mode Select is set
for Device mode, a single pull-up resistor on either D+ or D–,
determined by the LOA bit, will be enabled. See
details.
1: Enable pull-up/pull-down resistors
0: Disable pull-up/pull-down resistors
Table 23.USB Data Line Pull-up and Pull-down Resistors
Port A Force D± State (Bits [4:3])
The Port A Force D± State field controls the forcing state of the
D+ D– data lines for Port A. This field forces the state of the
Port A data lines independent of the Port Select bit setting. See
Table 24
L0A
X
X
1
0
for details.
Select
Mode
X
1
0
0
Resistors
Enable
Port n
0
1
1
1
Pull up/Pull down on D+ and
D– Disabled
Pull down on D+ and D–
Enabled
Pull up on USB D– Enabled
Pull up on USB D+ Enabled
Function
Table 23
for
Table 24.Port A Force D± State
Suspend Enable (Bit 2)
The Suspend Enable bit enables or disables the suspend
feature on both ports. When suspend is enabled the USB
transceivers are powered down and can not transmit or
received USB packets but can still monitor for a wakeup
condition.
1: Enable suspend
0: Disable suspend
Port A SOF/EOP Enable (Bit 0)
The Port A SOF/EOP Enable bit is only applicable in host
mode. In Device mode this bit must be written as ‘0’. In host
mode this bit enables or disables SOFs or EOPs for Port A.
Either SOFs or EOPs will be generated depending on the LOA
bit in the USB n Control Register when Port A is active.
1: Enable SOFs or EOPs
0: Disable SOFs or EOPs
Reserved
All reserved bits must be written as ‘0’.
USB Host Only Registers
There are twelve sets of dedicated registers to USB host only
operation. Each set consists of two identical registers (unless
otherwise noted); one for Host Port 1 and one for Host Port 2.
These register sets are covered in this section and summa-
rized in
Table 25.USB Host Only Register
Host n Control Register
Host n Address Register
Host n Count Register
Host n Endpoint Status Register
Host n PID Register
Host n Count Result Register
Host n Device Address Register
Host n Interrupt Enable Register
Host n Status Register
Host n SOF/EOP Count Register
Host n SOF/EOP Counter
Register
Host n Frame Register
Port A Force D± State
MSB
0
0
1
1
Table
Register Name
25.
LSB
0
1
0
1
Normal Operation
Force USB Reset, SE0 State
Force J-State
Force K-State
0xC08C/0xC0AC
0xC080/0xC0A0
0xC082/0xC0A2
0xC084/0xC0A4
0xC086/0xC0A6
0xC086/0xC0A6
0xC088/0xC0A8
0xC088/0xC0A8
0xC090/0xC0B0
0xC092/0xC0B2
0xC094/0xC0B4
0xC096/0xC0B6
(Host 1/Host 2)
Function
Address
CY7C67200
Page 19 of 78
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
R
R
R
R
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