CY7C67200-48BAXI Cypress Semiconductor Corp, CY7C67200-48BAXI Datasheet - Page 34

• Manufacturer Part Number: CY7C67200-48BAXI
• Description: USB HOST/PERIPH CNTRLR 48LFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-OTG™r
• Type: OTG Programmable USB On The Gor

Specifications of CY7C67200-48BAXI

• Package / Case: 48-LFBGA
• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 2.7 V ~ 3.6 V, 3 V ~ 3.6 V
• Current - Supply: 80mA, 135mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Operating Supply Voltage: 2.7 V to 3.6 V
• Controller Family/series: PSoC 1
• Core Size: 16 Bit
• No. Of I/o's: 25
• Program Memory Size: 16KB
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2262; CY7C67200-48BAXI

Document #: 38-08014 Rev. *G
Device n Interrupt Enable Register [R/W]
Register Description
The Device n Interrupt Enable register provides control over
device-related interrupts including eight different endpoint
interrupts.
VBUS Interrupt Enable (Bit 15)
The VBUS Interrupt Enable bit enables or disables the OTG
VBUS interrupt. When enabled this interrupt triggers on both
the rising and falling edge of VBUS at the 4.4V status (only
supported in Port 1A). This bit is only available for Device 1
and is a reserved bit in Device 2.
1: Enable VBUS interrupt
0: Disable VBUS interrupt
ID Interrupt Enable (Bit 14)
The ID Interrupt Enable bit enables or disables the OTG ID
interrupt. When enabled this interrupt triggers on both the
rising and falling edge of the OTG ID pin (only supported in
Port 1A). This bit is only available for Device 1 and is a
reserved bit in Device 2.
1: Enable ID interrupt
0: Disable ID interrupt
SOF/EOP Timeout Interrupt Enable (Bit 11)
The SOF/EOP Timeout Interrupt Enable bit enables or
disables the SOF/EOP Timeout Interrupt. When enabled this
interrupt triggers when the USB host fails to send a SOF or
EOP packet within the time period specified in the Device n
SOF/EOP Count register. In addition, the Device n Frame
register counts the number of times the SOF/EOP Timeout
Interrupt triggers between receiving SOF/EOPs.
1: SOF/EOP timeout occurred
0: SOF/EOP timeout did not occur
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
• Device 1 Interrupt Enable Register 0xC08C
• Device 2 Interrupt Enable Register 0xC0AC
EP7 Interrupt
Interrupt
Enable
VBUS
Enable
R/W
R/W
15
0
7
0
ID Interrupt
EP6 Interrupt
Enable
R/W
Enable
14
R/W
0
6
0
Figure 35. Device n Interrupt Enable Register
EP5 Interrupt
Enable
13
0
-
R/W
5
0
Reserved
EP4 Interrupt
12
Enable
0
-
R/W
4
0
SOF/EOP Interrupt Enable (Bit 9)
The SOF/EOP Interrupt Enable bit enables or disables the
SOF/EOP received interrupt.
1: Enable SOF/EOP Received interrupt
0: Disable SOF/EOP Received interrupt
Reset Interrupt Enable (Bit 8)
The Reset Interrupt Enable bit enables or disables the USB
Reset Detected interrupt
1: Enable USB Reset Detected interrupt
0: Disable USB Reset Detected interrupt
EP7 Interrupt Enable (Bit 7)
The EP7 Interrupt Enable bit enables or disables an endpoint
seven (EP7) Transaction Done interrupt. An EPx Transaction
Done interrupt triggers when any of the following responses or
events occur in a transaction for the device’s given Endpoint:
send/receive ACK, send STALL, Timeout occurs, IN Exception
Error, or OUT Exception Error. In addition, the NAK Interrupt
Enable bit in the Device n Endpoint Control register can also
be set so that NAK responses triggers this interrupt.
1: Enable EP7 Transaction Done interrupt
0: Disable EP7 Transaction Done interrupt
EP6 Interrupt Enable (Bit 6)
The EP6 Interrupt Enable bit enables or disables an endpoint
six (EP6) Transaction Done interrupt. An EPx Transaction
Done interrupt triggers when any of the following responses or
events occur in a transaction for the device’s given Endpoint:
send/receive ACK, send STALL, Timeout occurs, IN Exception
Error, or OUT Exception Error. In addition, the NAK Interrupt
Enable bit in the Device n Endpoint Control register can also
be set so that NAK responses triggers this interrupt.
1: Enable EP6 Transaction Done interrupt
0: Disable EP6 Transaction Done interrupt
Interrupt Enable
EP3 Interrupt
SOF/EOP
Timeout
Enable
R/W
R/W
11
0
3
0
EP2 Interrupt
Reserved
Enable
R/W
2
0
10
0
-
EP1 Interrupt
SOF/EOP
Interrupt
Enable
Enable
R/W
R/W
1
0
9
0
CY7C67200
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EP0 Interrupt
Interrupt
Enable
Enable
Reset
R/W
R/W
0
0
8
0
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