CY7C67200-48BAXI Cypress Semiconductor Corp, CY7C67200-48BAXI Datasheet - Page 38

• Manufacturer Part Number: CY7C67200-48BAXI
• Description: USB HOST/PERIPH CNTRLR 48LFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-OTG™r
• Type: OTG Programmable USB On The Gor

Specifications of CY7C67200-48BAXI

• Package / Case: 48-LFBGA
• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 2.7 V ~ 3.6 V, 3 V ~ 3.6 V
• Current - Supply: 80mA, 135mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Operating Supply Voltage: 2.7 V to 3.6 V
• Controller Family/series: PSoC 1
• Core Size: 16 Bit
• No. Of I/o's: 25
• Program Memory Size: 16KB
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2262; CY7C67200-48BAXI

Document #: 38-08014 Rev. *G
Device n Frame Number Register [R]
Register Description
The Device n Frame Number register is a read only register
that contains the Frame number of the last SOF packet
received. This register also contains a count of SOF/EOP
Timeout occurrences.
SOF/EOP Timeout Flag (Bit 15)
The SOF/EOP Timeout Flag bit indicates when an SOF/EOP
Timeout Interrupt occurs.
1: An SOF/EOP Timeout interrupt occurred
0: An SOF/EOP Timeout interrupt did not occur
Device n SOF/EOP Count Register [W]
Register Description
The Device n SOF/EOP Count register must be written with
the time expected between receiving a SOF/EOPs. If the
SOF/EOP counter expires before an SOF/EOP is received, an
SOF/EOP Timeout Interrupt can be generated. The SOF/EOP
Timeout Interrupt Enable and SOF/EOP Timeout Interrupt
Flag are located in the Device n Interrupt Enable and Status
registers, respectively.
The SOF/EOP count must be set slightly greater than the
expected SOF/EOP interval. The SOF/EOP counter decre-
ments at a 12-MHz rate. Therefore in the case of an expected
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
• Device 1 Frame Number Register 0xC092
• Device 2 Frame Number Register 0xC0B2
• Device 1 SOF/EOP Count Register 0xC094
• Device 2 SOF/EOP Count Register 0xC0B4
Timeout Flag
SOF/EOP
15
15
R
R
R
0
7
0
0
7
1
-
Reserved
14
14
R
R
R
0
6
0
0
6
1
-
Timeout Interrupt Counter
Figure 39. Device n SOF/EOP Count Register
Figure 38. Device n Frame Number Register
SOF/EOP
13
13
R
R
R
R
0
5
0
1
5
1
12
12
R
R
R
R
0
4
0
0
4
0
SOF/EOP Timeout Interrupt Counter (Bits [14:12])
The SOF/EOP Timeout Interrupt Counter field increments by
1 from 0 to 7 for each SOF/EOP Timeout Interrupt. This field
resets to 0 when a SOF/EOP is received. This field is only
updated when the SOF/EOP Timeout Interrupt Enable bit in
the Device n Interrupt Enable register is set.
Frame (Bits [10:0])
The Frame field contains the frame number from the last
received SOF packet in full speed mode. This field has no
function for low-speed mode. If a SOF Timeout occurs, this
field contains the last received Frame number.
1-ms SOF/EOP interval, the SOF/EOP count must be set
slightly greater then 0x2EE0.
Count (Bits [13:0])
The Count field contains the current value of the SOF/EOP
down counter. At power-up and reset, this value is set to
0x2EE0 and for expected 1-ms SOF/EOP intervals, this
SOF/EOP count should be increased slightly.
Reserved
All reserved bits must be written as ‘0’.
...Frame
...Count
Reserved
11
11
R
R
R
0
3
0
1
3
0
-
Count...
10
10
R
R
R
R
0
2
0
1
2
0
Frame...
R
R
R
R
9
0
1
0
9
1
1
0
CY7C67200
Page 38 of 78
R
R
R
R
8
0
0
0
8
0
0
0
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