MSC8113TMP3600V Freescale Semiconductor, MSC8113TMP3600V Datasheet - Page 23

• Manufacturer Part Number: MSC8113TMP3600V
• Description: DSP TRI-CORE 431-FCPBGA
• Manufacturer: Freescale Semiconductor
• Series: MSC81xx StarCorer
• Type: SC140 Corer

Specifications of MSC8113TMP3600V

• Interface: Ethernet, I²C, TDM, UART
• Clock Rate: 300MHz
• Non-volatile Memory: External
• On-chip Ram: 1.436MB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.10V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 431-FCPBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Freescale Semiconductor
Notes:
No.
32a
32b
32c
32d
33a
33b
35a
35b
30
31
34
2
1.
2.
3.
Minimum delay from the 50% level of the REFCLK for all signals
PSDVAL/TEA/TA max delay from the 50% level of the REFCLK rising edge
Address bus max delay from the 50% level of the REFCLK rising edge
•
•
Address attributes: TT[0–1]/TBST/TSZ/GBL max delay from the 50% level
of the REFCLK rising edge
Address attributes: TT[2–4]/TC max delay from the 50% level of the
REFCLK rising edge
BADDR max delay from the 50% level of the REFCLK rising edge
Data bus max delay from the 50% level of the REFCLK rising edge
•
•
DP max delay from the 50% level of the REFCLK rising edge
•
•
Memory controller signals/ALE/CS[0–4] max delay from the 50% level of
the REFCLK rising edge
DBG/BG/BR/DBB max delay from the 50% level of the REFCLK rising
edge
AACK/ABB/TS/CS[5–7] max delay from the 50% level of the REFCLK
rising edge
Multi-master mode (SIUBCR[EBM] = 1)
Single-master mode (SIUBCR[EBM] = 0)
Data-pipeline mode
Non-pipeline mode
Data-pipeline mode
Non-pipeline mode
Values are measured from the 50% level of the REFCLK rising edge to the 50% signal level and assume a 20 pF load except
where otherwise specified.
Except for specification 30, which is specified for a 10 pF load, all timings in this table are specified for a 20 pF load.
Decreasing the load results in a timing decrease at the rate of 0.3 ns per 5 pF decrease in load. Increasing the load results in
a timing increase at the rate of 0.15 ns per 5 pF increase in load.
The maximum bus frequency depends on the mode:
• In 60x-compatible mode connected to another MSC8113 device, the frequency is determined by adding the input and output
longest timing values, which results in the total delay for 20 pF output capacitance. You must also account for other
influences that can affect timing, such as on-board clock skews, on-board noise delays, and so on.
• In single-master mode, the frequency depends on the timing of the devices connected to the MSC8113.
• To achieve maximum performance on the bus in single-master mode, disable the DBB signal by writing a 1 to the
SIUMCR[BDD] bit. See the SIU chapter in the MSC8113 Reference Manual for details.
MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 1
Characteristic
Table 15. AC Timing for SIU Outputs
Ref = CLKIN at 1.1 V
Bus Speed in MHz
and 100/ 133 MHz
0.9
6.0
6.4
5.3
6.4
6.9
5.2
4.8
7.1
6.0
7.5
5.1
6.0
5.5
Electrical Characteristics
3
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
23