MSC8113TMP3600V Freescale Semiconductor, MSC8113TMP3600V Datasheet - Page 16

• Manufacturer Part Number: MSC8113TMP3600V
• Description: DSP TRI-CORE 431-FCPBGA
• Manufacturer: Freescale Semiconductor
• Series: MSC81xx StarCorer
• Type: SC140 Corer

Specifications of MSC8113TMP3600V

• Interface: Ethernet, I²C, TDM, UART
• Clock Rate: 300MHz
• Non-volatile Memory: External
• On-chip Ram: 1.436MB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.10V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 431-FCPBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Electrical Characteristics
2.5
The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs. When
systems such as DSP farms are developed using the DSI, use a device loading of 4 pF per pin. AC timings are based on a 20 pF
load, except where noted otherwise, and a 50 Ω transmission line. For loads smaller than 20 pF, subtract 0.06 ns per pF down
to 10 pF load. For loads larger than 20 pF, add 0.06 ns for SIU/Ethernet/DSI delay and 0.07 ns for GPIO/TDM/timer delay.
When calculating overall loading, also consider additional RC delay.
2.5.1
2.5.2
Starting the device requires coordination among several input sequences including clocking, reset, and power. Section 2.5.3
describes the clocking characteristics. Section 2.5.4 describes the reset and power-up characteristics. You must use the
following guidelines when starting up an MSC8113 device:
The following figures show acceptable start-up sequence examples. Figure 6 shows a sequence in which
raised together. Figure 7 shows a sequence in which
16
System bus
Memory controller
Parallel I/O
Note:
•
•
•
•
PORESET
If possible, bring up the
levels and then the
CLKIN
deassertion to guarantee correct device operation (see Figure 6 and Figure 7).
CLKIN
These are typical values at 65°C. The impedance may vary by ±25% depending on device process and operating temperature.
AC Timings
Output Buffer Impedances
Start-Up Timing
should start toggling at least 16 cycles (starting after
must not be pulled high during
and
Output Buffers
TRST
o.5 V
1.1 V
2.2 V
3.3 V
Figure 6. Start-Up Sequence: V
V
DDH
MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 1
must be asserted externally for the duration of the power-up sequence. See Table 11 for timing.
V
levels (see Figure 7).
DD
and
PORESET/TRST Asserted
V
DD
Table 6. Output Buffer Impedances
V
/V
DDH
CLKIN Starts Toggling
DDH
V
levels together. For designs with separate power supplies, bring up the
DDH
Applied
V
power-up.
DDH
is raised after
V
V
DD
CLKIN
DDH
DD
1
= Nominal Value
and V
= Nominal Value
V
DDH
can toggle during this period.
V
DDH
DD
reaches its nominal level) before
PORESET/TRST Deasserted
and
Raised Together
CLKIN
Typical Impedance (Ω)
begins to toggle as
V
V
DD
DDH
50
50
50
Nominal Level
Time
Nominal Level
Freescale Semiconductor
V
DD
PORESET
V
and
DDH
V
rises.
DDH
V
are
DD