MSC8113TMP3600V Freescale Semiconductor, MSC8113TMP3600V Datasheet - Page 21

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MSC8113TMP3600V

Manufacturer Part Number
MSC8113TMP3600V
Description
DSP TRI-CORE 431-FCPBGA
Manufacturer
Freescale Semiconductor
Series
MSC81xx StarCorer
Type
SC140 Corer
Datasheet

Specifications of MSC8113TMP3600V

Interface
Ethernet, I²C, TDM, UART
Clock Rate
300MHz
Non-volatile Memory
External
On-chip Ram
1.436MB
Voltage - I/o
3.30V
Voltage - Core
1.10V
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
431-FCPBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MSC8113TMP3600V
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
2.5.5
2.5.5.1
Generally, all MSC8113 bus and system output signals are driven from the rising edge of the reference clock (REFCLK). The
REFCLK is the
is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge of REFCLK (and T3 at the falling
edge), but the spacing of T2 and T4 depends on the PLL clock ratio selected, as Table 13 shows.
Figure 10 is a graphical representation of Table 13.
Freescale Semiconductor
BCLK/SC140 clock
1:4, 1:6, 1:8, 1:10
Output (I/O)
Output (I/O)
PORESET
HRESET
SRESET
System Bus Access Timing
PORESET
1:3
1:5
Input
Internal
CLKIN
Core Data Transfers
REFCLK
REFCLK
REFCLK
signal. Memory controller signals, however, trigger on four points within a REFCLK cycle. Each cycle
Figure 10. Internal Tick Spacing for Memory Controller Signals
T1
T1
T1
Figure 9. Timing Diagram for a Reset Configuration Write
MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 1
Table 13. Tick Spacing for Memory Controller Signals
1
T2
T2
T2
Reset configuration write
sequence during this
period.
2/10 REFCLK
1/4 REFCLK
1/6 REFCLK
RSTCONF, CNFGS, DSISYNC, DSI64
CHIP_ID[0–3], BM[0–2], SWTE, MODCK[1–2]
pins are sampled
Reset Configuration
T2
Host programs
T3
T3
T3
Tick Spacing (T1 Occurs at the Rising Edge of REFCLK)
1 + 2
Word
2
T4
T4
T4
SPLL
locking period
MODCK[3–5]
1/2 REFCLK
1/2 REFCLK
1/2 REFCLK
3
T3
for 1:3
for 1:5
for 1:4, 1:6, 1:8, 1:10
SPLL is locked
(no external indication)
Electrical Characteristics
5
6
7/10 REFCLK
3/4 REFCLK
4/6 REFCLK
T4
21

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