MSC8122TVT6400V Freescale Semiconductor, MSC8122TVT6400V Datasheet
MSC8122TVT6400V
Specifications of MSC8122TVT6400V
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MSC8122TVT6400V Summary of contents
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... Flexible memory controller with three UPMs, a GPCM, a page-mode SDRAM machine, glueless interface to a variety of memories and devices, byte enables for 64- or 32-bit bus widths, © Freescale Semiconductor, Inc., 2004, 2008. All rights reserved. Document Number: MSC8122 MSC8122 FC PBGA–431 20 mm × ...
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... Figure 30.Boundary Scan (JTAG) Timing Diagram . . . . . . . . . . . . 38 Figure 31.Test Access Port Timing Diagram . . . . . . . . . . . . . . . . . 39 Figure 32.TRST Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 39 and Figure 33.Core Power Supply Decoupling Raised Together . . 17 Figure 34.V CCSYN with CLKIN Figure 35.MSC8122 Mechanical Information, 431-pin FC-PBGA DDH Package CCSYN Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Freescale Semiconductor ...
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... The QBus interface includes a bus switch, write buffer, fetch unit, and a control unit that defines four QBus banks. In addition, the QBC handles internal memory contentions. Figure 2. StarCore SC140 DSP Extended Core Block Diagram MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor SC140 SC140 Extended Core ...
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... This section includes diagrams of the MSC8122 package ball grid array layouts and pinout allocation tables. 1.1 FC-PBGA Ball Layout Diagrams Top and bottom views of the FC-PBGA package are shown in Figure 3 and Figure 4 with their ball location index numbers. MSC8122 Quad Digital Signal Processor Data Sheet, Rev Freescale Semiconductor ...
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... HD4 GND GND V DDH HD7 HD15 HD9 HD60 DDH HD14 HD12 HD10 HD63 HD59 DD AB GND HD13 HD11 HD8 HD62 HD61 MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor Top View GND GND GND GND GND GND HCID3 GND ...
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... GND GND HD4 DDH DDH GND HD58 HD60 HD9 DDH DD V GND HD59 HD63 HD10 HD12 DDH HD56 HD57 HD61 HD62 HD8 HD11 Freescale Semiconductor GND DD EE0 TDI TRST TCK RST PO CONF RESET HA27 HA24 HA28 HA20 DD HA26 HA18 DD HA21 HA15 ...
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... GND C11 V DD C12 GND C13 V DD C14 GND C15 GND C16 GPIO30/TIMER2/TMCLK/SDA C17 GPIO2/TIMER1/CHIP_ID2/IRQ6 MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor Des. Signal Name C18 GPIO1/TIMER0/CHIP_ID1/IRQ5/ETHTXD1 C19 GPIO7/TDM3RCLK/IRQ5/ETHTXD3 C20 GPIO3/TDM3TSYN/IRQ1/ETHTXD2 C21 GPIO5/TDM3TDAT/IRQ3/ETHRXD3 C22 GPIO6/TDM3RSYN/IRQ4/ETHRXD2 D2 TDI D3 EE0 D4 EE1 ...
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... CS1 G18 BCTL0 G19 GPIO15/TDM1TSYN/DREQ1 G20 GND G21 GPIO17/TDM1TDAT/DACK1 G22 GPIO22/TDM0TCLK/DONE2/DRACK2 H2 HA20 H3 HA28 HA19 H6 TEST H7 PSDCAS/PGPL3 H8 PGTA/PUPMWAIT/PGPL4/PPBS H10 BM1/TC1/BNKSEL1 H11 ARTRY H12 AACK H13 DBB/IRQ5 H14 HTA H15 V DD H16 TT4/CS7 H17 CS4 H18 GPIO24/TDM0RSYN/IRQ14 H19 GPIO21/TDM0TSYN H20 V DD Freescale Semiconductor ...
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... PWE1/PSDDQM1/PBS1 K7 POE/PSDRAS/PGPL2 K8 IRQ2/BADDR30 K9 Reserved K10 GND K11 GND K12 GND K13 GND K14 CLKOUT MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor Des. Signal Name K15 V DD K16 TT2/CS5 K17 ALE K18 CS2 K19 GND K20 A26 K21 A29 ...
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... A19 R2 HD18 R3 V DDH R4 GND R5 HD22 R6 HWBS6/HDBS6/HWBE6/HDBE6/PWE6/PSDDQM6/PBS6 R7 HWBS4/HDBS4/HWBE4/HDBE4/PWE4/PSDDQM4/PBS4 R8 TSZ1 R9 TSZ3 R10 IRQ1/GBL R11 V DD R12 V DD R13 V DD R14 TT0/HA7 R15 IRQ7/DP7/DREQ4 R16 IRQ6/DP6/DREQ3 R17 IRQ3/DP3/DREQ2/EXT_BR3 R18 TS R19 IRQ2/DP2/DACK2/EXT_DBG2 R20 A17 R21 A18 R22 A16 T2 HD17 T3 HD21 T4 HD1/DSISYNC T5 HD0/SWTE Freescale Semiconductor ...
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... U11 D14 U12 D15 U13 D17 U14 D19 U15 D22 U16 D25 U17 D26 U18 D28 U19 D31 U20 V DDH MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor Des. Signal Name U21 A12 U22 A13 V2 HD3/MODCK1 V3 V DDH V4 GND ...
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... AB3 HD13 AB4 HD11 AB5 HD8 AB6 HD62/D62 AB7 HD61/D61 AB8 HD57/D57/ETHRX_ER AB9 HD56/D56/ETHRX_DV/ETHCRS_DV AB10 HD55/D55/ETHTX_ER/reserved AB11 HD53/D53 AB12 HD50/D50 AB13 HD49/D49/ETHTXD3/reserved AB14 HD48/D48/ETHTXD2/reserved AB15 HD47/D47/ETHTXD1 AB16 HD45/D45 AB17 HD44/D44 AB18 HD41/D41/ETHRXD1 AB19 HD39/D39/reserved AB20 HD36/D36/reserved AB21 A1 AB22 V DD Freescale Semiconductor ...
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... Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the listed limits may affect device reliability or cause permanent damage. 3. Section 3.5, Thermal Considerations includes a formula for computing the chip junction temperature (T MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor CAUTION ). DD Table 2. Absolute Maximum Ratings ...
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... V 3.135 to 3.465 DDH V –0 –40 to 105 J FC-PBGA × Symbol Natural Convection (1 m/s) airflow R 26 θ θ θJB R 0.9 θJC Ψ Unit +0.2 V DDH °C °C 5 Unit 200 ft/min 21 °C/W 15 °C/W °C/W °C/W °C/W Freescale Semiconductor ...
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... To assure proper board design with regard to thermal dissipation and maintaining proper operating temperatures, evaluate power consumption for your application and use the design guidelines in Chapter 4 of this document and in MSC8102, MSC8122, and MSC8126 Thermal Management Design Guidelines (AN2601). MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor and ...
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... For designs with separate power supplies, bring up the V DDH reaches its nominal level) before V DDH V power-up. CLKIN can toggle during this period. DDH V is raised after V DDH DD and Typical Impedance (Ω PORESET V and V DD DDH and CLKIN begins to toggle as V rises. DDH Freescale Semiconductor V DD are ...
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... V 2.2 V 1.2 V o.5 V Figure 6. Start-Up Sequence: V 3.3 V 1.2 V o.5 V PORESET/TRST asserted V applied DD Figure 7. Start-Up Sequence: V MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor V = Nominal Value DDH V = Nominal Value DD 1 PORESET/TRST Deasserted CLKIN Starts Toggling PORESET/TRST Asserted V /V Applied ...
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... CLKOUT F 200 300 CORE (IO) t (time CCSYN / voltage level CCSYN Maximum in MHz 300/400/500 100/133/166 100/133/166 100/133/166 400 MHz Device 500 MHz Device Min Max Min Max 20 133.3 20 166.7 40 133.3 40 166.7 40 133.3 40 166.7 40 133.3 40 166.7 200 400 200 Freescale Semiconductor 500 ...
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... When a host reset command is written through the Test Access Port (TAP), the TAP logic asserts the command through soft reset signal and an internal soft reset sequence is generated. the TAP MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor Table 9. System Clock Parameters ) Table 10. Reset Sources Description ...
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... Yes Yes Yes Yes Yes Yes Yes PORESET must be asserted externally for at least 16 Soft Reset (SRESET) JTAG Command: External EXTEST, CLAMP, or HIGHZ Yes Yes Yes Depends on command Yes Yes Yes Yes CLKIN cycles after PORESET deassertion to define the Reset Freescale Semiconductor ...
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... HRESET Output (I/O) SRESET Output (I/O) Figure 9. Timing Diagram for a Reset Configuration Write MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor , CNFGS, DSISYNC, DSI64, RSTCONF , RSTCONF, CNFGS, DSISYNC, DSI64 CHIP_ID[0–3], BM[0–2], SWTE, MODCK[1–2] pins are sampled ...
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... MSC8122 Quad Digital Signal Processor Data Sheet, Rev Tick Spacing (T1 Occurs at the Rising Edge of REFCLK) T2 1/4 REFCLK 1/2 REFCLK 1/6 REFCLK 1/2 REFCLK 2/10 REFCLK 1/2 REFCLK 3/4 REFCLK 4/6 REFCLK 7/10 REFCLK for 1:4, 1:6, 1:8, 1:10 for 1:3 for 1:5 Freescale Semiconductor ...
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... Values are measured from the 50% TTL transition level relative to the 50% level of the REFCLK rising edge. 3. Guaranteed by design. MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor Table 14. AC Timing for SIU Inputs Value for Bus Speed in MHz Ref = CLKIN 1.1 V ...
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... Freescale Semiconductor ...
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... Data bus inputs—ECC and parity modes Address bus/TS /TT[0–4]/TC[0–2]/ TBST/TSZ[0–3]/GBL inputs Address bus/TT[0–4]/TC[0–2]/TBST/TSZ[0–3]/GBL outputs Memory controller/ALE outputs AACK/ABB/TS/DBG/BG/BR/DBB/CS outputs MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor REFCLK 11 PSDVAL/ABB/DBB inputs inputs ...
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... Table 16. CLKOUT Skew CLKIN CLKOUT 20 Figure 12. CLKOUT and CLKIN Signals Min Max Units 0.0 0.95 ns 0.0 0.85 ns –1.5 1.0 ns –0.8 1.0 ns 2.8 — ns 2.8 — ns 2.2 — ns 2.2 — ns 3.3 — ns 3.3 — ns and timings. CLKOUT CLKIN 21 Freescale Semiconductor ...
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... DACK/DRACK/DONE delay after the 50% level of the REFCLK rising edge signal is synchronized with The DREQ according to the timings in Table 17. Figure 13 shows synchronous peripheral interaction. DACK/DONE/DRACK MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor Table 17. DMA Signals . To achieve fast response, a synchronized peripheral should assert REFCLK REFCLK 37 ...
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... T ) REFCLK 1 REFCLK — 8.5 2.0 — 2.2 — 2.2 — 3.2 — — 7.4 — 6.7 — 6.5 — 6.5 — REFCLK 5 + (1.5 × REFCLK 5 + (2.5 × REFCLK 1 — REFCLK 1.0 — 1.7 — 1.5 — Freescale Semiconductor Unit ...
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... HTA released at logic 0 (DCR[HTAAD end of access; used with pull-down implementation. 4. HTA released at logic 1 (DCR[HTAAD end of access; used with pull-up implementation. Figure 14. Asynchronous Single- and Dual-Strobe Modes Read Timing Diagram MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor 100 101 112 102 103 107 ...
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... Used for single-strobe mode access. 2. Used for dual-strobe mode access. Figure 16. Asynchronous Broadcast Write Timing Diagram MSC8122 Quad Digital Signal Processor Data Sheet, Rev 100 112 201 106 108 100 112 201 202 101 102 202 109 110 111 101 102 Freescale Semiconductor ...
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... All other input signals HD[0–63] output signals HTA output signal Figure 17. DSI Synchronous Mode Signals Timing Diagram MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor Table 19. DSI Inputs in Synchronous Mode Expression HTC (0.5 ± 0.1) × HTC (0.5 ± 0.1) × HTC — ...
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... Freescale Semiconductor ...
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... URXD and UTXD inputs high/low duration 401 URXD and UTXD inputs rise/fall time 402 UTXD output rise/fall time UTXD, URXD inputs UTXD output MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor Table 22. UART Timing Expression 16 × T 401 401 400 Figure 20. UART Input Timing 402 402 Figure 21 ...
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... MSC8122 Quad Digital Signal Processor Data Sheet, Rev Table 23. Timer Timing Characteristics 500 501 502 503 Figure 22. Timer Timing Characteristics 801 802 Valid Ref = CLKIN Unit Min Max 10.0 — ns 4.0 — ns 4.0 — ns 3.1 9.5 ns 2.8 8.1 ns Min Max Unit 10 — — ns Freescale Semiconductor ...
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... ETHREF_CLK rising edge to ETHTXD[0–1], ETHTX_EN output delay. ETHREF_CLK ETHCRS_DV ETHRXD[0–1] ETHRX_ER ETHTX_EN ETHTXD[0–1] MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor Table 25. MII Mode Signal Timing Characteristics 803 Valid 805 Valid Figure 24. MII Mode Signal Timing Table 26 ...
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... Valid Ref = CLKOUT Ref = CLKIN (1.2 V only) Unit Min Max Min Max — 6.1 — 6.9 ns 1.1 — 1.3 — ns — 5.4 — 6.2 ns 3.5 — 3.7 — ns 0.5 — 0.5 — ns Freescale Semiconductor ...
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... TCK clock pulse width measured at V • High • Low 703 TCK rise and fall times MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor High Impedance 604 605 Valid Figure 27. GPIO Timing Table 29. EE Pin Timing Type Asynchronous ...
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... Input Data Valid 706 Output Data Valid 707 All frequencies Unit Min Max 5.0 — 20.0 — 0.0 30.0 0.0 30.0 5.0 — 20.0 — 0.0 20.0 0.0 20.0 100.0 — 30.0 — 702 V M 703 V IH 705 Freescale Semiconductor ...
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... DD device ESD protection circuits to the V by more than 0.8 V. Design the power supply to prevent or minimize this effect using one of the following optional methods: MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor 708 Input Data Valid 710 Output Data Valid ...
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... Pull up all unused inputs or signals that will be inputs during reset max One 0.01 µF capacitor for every 3 core supply MSC8122 pads. High frequency capacitors (very low ESR and ESL and GND CC DD input with a circuit similar to the one in CCSYN Freescale Semiconductor should V and CC ...
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... EXT_BR[2–3] EXT_BG[2–3] functionality. • In single-master mode, and ABB modes, they must be pulled up. MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor V 10Ω 10nH 10 µF Figure 34. V Bypass CCSYN HCS and HBCS must pulled up and all the rest of the DSI signals can be HTA must be pulled up ...
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... CLKOUT CLKOUT must not exceed 10 pF. (if SIUMCR[INTODC] is cleared), NMI_OUT PPBS can be disconnected. Otherwise and RSTCONF BM[0–2] signal. Therefore, they should PORESET signal. PORESET , and (if not full drive) signals must IRQxx and must not be connected GPIO10 GPIO14 Freescale Semiconductor are ...
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... Core Operating Frequency Voltage Temperature (MHz) 1.1 V –40° to 105°C 300 400 1.2 V –40° to 105°C 400 0° to 90°C 500 Ordering Information Eqn with natural Eqn. 2 Order Number Lead-Free Lead-Bearing MSC8122TVT4800V MSC8122TMP4800V MSC8122TVT6400V MSC8122TMP6400V MSC8122TVT6400 MSC8122TMP6400 MSC8122VT8000 MSC8122MP8000 43 ...
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... Capacitors may not be present on all devices. 8. Caution must be taken not to short capacitors or exposed metal capacitor pads on package top CBGA (Ceramic) package code: 5238. FC PBGA (Plastic) package code: 5263. 10.Pin 1 indicator can be in the form of number 1 marking or an “L” shape marking. Freescale Semiconductor ...
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... Added connectivity guidelines for DSI in sliding windows mode to Section 3.3. 15 May 2008 • Changed V 16 Dec. 2008 • Clarified the wording of note 2 in Table 24. MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor Table 31. Document Revision History Description 2 C timing changed to GPIO timing. . DDH + 8% in Figure 2-1. ...
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... Revision History MSC8122 Quad Digital Signal Processor Data Sheet, Rev Freescale Semiconductor ...
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... MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor Revision History 47 ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...