DSPB56362AG120 Freescale Semiconductor, DSPB56362AG120 Datasheet - Page 50

• Manufacturer Part Number: DSPB56362AG120
• Description: IC DSP 24BIT AUD 120MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56362AG120

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 120MHz
• Non-volatile Memory: ROM (126 kB)
• On-chip Ram: 42kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 120MHz
• Mips: 120
• Device Input Clock Speed: 120MHz
• Ram Size: 42KB
• Program Memory Size: 90KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.46V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Product: DSPs
• Data Bus Width: 24 bit
• Processor Series: DSP563xx
• Core: 56000
• Numeric And Arithmetic Format: Fixed-Point
• Instruction Set Architecture: Modified Harvard
• Device Million Instructions Per Second: 120 MIPS
• Maximum Clock Frequency: 120 MHz
• Program Memory Type: Flash
• Data Ram Size: 42 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface Type: SPI, I2C, ESAI, SHI
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

External Memory Expansion Port (Port A)
3-24
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
No.
Page mode cycle time for two consecutive accesses
of the same direction
Page mode cycle time for mixed (read and write)
accesses.
CAS assertion to data valid (read)
Column address valid to data valid (read)
CAS deassertion to data not valid (read hold time)
Last CAS assertion to RAS deassertion
Previous CAS deassertion to RAS deassertion
CAS assertion pulse width
Last CAS deassertion to RAS assertion
BRW[1:0] = 00
BRW[1:0] = 01
BRW[1:0] = 10
BRW[1:0] = 11
CAS deassertion pulse width
Column address valid to CAS assertion
CAS assertion to column address not valid
Last column address valid to RAS deassertion
WR deassertion to CAS assertion
CAS deassertion to WR assertion
CAS assertion to WR deassertion
WR assertion pulse width
Last WR assertion to RAS deassertion
WR assertion to CAS deassertion
Table 3-12 DRAM Page Mode Timings, Four Wait States 100 and 120MHz
Characteristics
DSP56362 Technical Data, Rev. 4
5
Symbol
t
t
t
t
RHCP
t
t
t
t
t
t
t
t
t
t
WCH
t
RSH
CRP
CAH
RCS
RCH
RWL
CWL
t
CAC
t
OFF
CAS
t
ASC
RAL
WP
PC
AA
CP
2.75 × T
3.75 × T
2.75 × T
4.25 × T
5.25 × T
7.25 × T
1.25 × T
3.25 × T
3.75 × T
1.25 × T
4.75 × T
3.5 × T
2.5 × T
3.5 × T
4.5 × T
Expression
6 × T
2 × T
5 × T
100 MHz:
100 MHz:
100 MHz:
100 MHz:
T
4.5 × T
5 × T
C
C
C
− 4.0
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
− 4.0
− 4.0
− 4.0
C
− 4.0
− 4.0
− 4.0
− 4.5
− 7.0
− 7.0
− 6.0
− 6.0
− 6.0
− 6.0
− 4.0
− 4.2
− 4.3
− 4.3
C
− 4.0
50.0
45.0
31.0
56.0
21.0
46.5
66.5
16.0
31.0
46.0
28.3
40.5
43.2
33.2
Min
0.0
6.0
8.5
8.5
—
—
—
—
100 MHz
Max
20.5
30.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Freescale Semiconductor
1, 2, 3, 4
41.7
37.5
25.2
46.0
16.8
37.7
54.4
12.7
25.2
37.7
22.9
33.0
35.3
26.9
Min
0.0
4.3
6.4
6.4
—
—
—
—
120 MHz
Max
15.9
24.2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns