DSPB56362AG120 Freescale Semiconductor, DSPB56362AG120 Datasheet - Page 32

• Manufacturer Part Number: DSPB56362AG120
• Description: IC DSP 24BIT AUD 120MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56362AG120

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 120MHz
• Non-volatile Memory: ROM (126 kB)
• On-chip Ram: 42kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 120MHz
• Mips: 120
• Device Input Clock Speed: 120MHz
• Ram Size: 42KB
• Program Memory Size: 90KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.46V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Product: DSPs
• Data Bus Width: 24 bit
• Processor Series: DSP563xx
• Core: 56000
• Numeric And Arithmetic Format: Fixed-Point
• Instruction Set Architecture: Modified Harvard
• Device Million Instructions Per Second: 120 MIPS
• Maximum Clock Frequency: 120 MHz
• Program Memory Type: Flash
• Data Ram Size: 42 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface Type: SPI, I2C, ESAI, SHI
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Phase Lock Loop (PLL) Characteristics
3.8
3-6
1
1
2
3
4
5
6
V
PLL external capacitor (PCAP pin to V
Note:
• @ MF ≤ 4
• @ MF > 4
No.
CO
C
C
Measured at 50% of the input transition.
The maximum value for PLL enabled is given for minimum V
The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low
time required for correction operation, however, remains the same at lower operating frequencies; therefore, when a lower
clock frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and
low time requirements are met.
Periodically sampled and not 100% tested.
The skew is not guaranteed for any other MF value.
The maximum value for PLL enabled is given for minimum V
6
7
PCAP
PCAP
frequency when PLL enabled (MF × E
(680 × MF) – 120, for MF ≤ 4, or
1100 × MF, for MF > 4
CLKOUT rising edge from EXTAL rising edge with PLL
enabled (MF = 1, PDF = 1, Ef > 15 MHz)
CLKOUT falling edge from EXTAL rising edge with PLL
enabled (MF = 2 or 4, PDF = 1, Ef > 15 MHz)
CLKOUT falling edge from EXTAL falling edge with PLL
enabled (MF ≤ 4, PDF ≠ 1, Ef / PDF > 15 MHz)
Instruction cycle time = I
See
• With PLL disabled
• With PLL enabled
is the value of the PLL capacitor (connected between the PCAP pin and V
can be computed from one of the following equations:
Phase Lock Loop (PLL) Characteristics
Table 3-5
Characteristics
Table 3-5 Clock Operation (continued) 100 and 120 MHz Values
(46.7%–53.3% duty cycle)
Characteristics
CYC
= T
CCP
C
6
) (C
f
× 2/PDF)
Table 3-6 PLL Characteristics
DSP56362 Technical Data, Rev. 4
PCAP
4, 5
)
1
4, 5
4, 5
(MF × 580) − 100
CO
CO
and maximum MF.
and maximum DF.
MF × 830
Min
30
Symbol
I
CYC
100 MHz
CCP
0.00 ns
0.00 ns
0.0 ns
0.0 ns
0.0 ns
Min
). The recommended value in pF for
100 MHz
(MF × 780) − 140
MF × 1470
8.53 µs
1.8 ns
1.8 ns
1.8 ns
Max
Max
200
∞
Freescale Semiconductor
Min
120 MHz
8.53 µs
MHz
Unit
Max
pF
pF