DSPB56362AG120 Freescale Semiconductor, DSPB56362AG120 Datasheet - Page 12

• Manufacturer Part Number: DSPB56362AG120
• Description: IC DSP 24BIT AUD 120MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56362AG120

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 120MHz
• Non-volatile Memory: ROM (126 kB)
• On-chip Ram: 42kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 120MHz
• Mips: 120
• Device Input Clock Speed: 120MHz
• Ram Size: 42KB
• Program Memory Size: 90KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.46V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Product: DSPs
• Data Bus Width: 24 bit
• Processor Series: DSP563xx
• Core: 56000
• Numeric And Arithmetic Format: Fixed-Point
• Instruction Set Architecture: Modified Harvard
• Device Million Instructions Per Second: 120 MIPS
• Maximum Clock Frequency: 120 MHz
• Program Memory Type: Flash
• Data Ram Size: 42 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface Type: SPI, I2C, ESAI, SHI
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

External Memory Expansion Port (Port A)
2.5.3
2-6
Signal Name
AA0–AA3/RA
S0–RAS3
CAS
WR
RD
TA
External Bus Control
Output
Output
Output
Output
Type
Input
State during Reset
Ignored Input
Tri-Stated
Tri-Stated
Tri-Stated
Tri-Stated
Table 2-7 External Bus Control Signals
DSP56362 Technical Data, Rev. 4
Address Attribute or Row Address Strobe—When defined as AA, these
signals can be used as chip selects or additional address lines. When
defined as RAS, these signals can be used as RAS for DRAM interface.
These signals are can be tri-stated outputs with programmable polarity.
Column Address Strobe—When the DSP is the bus master, CAS is an
active-low output used by DRAM to strobe the column address. Otherwise,
if the bus mastership enable (BME) bit in the DRAM control register is
cleared, the signal is tri-stated.
Read Enable—When the DSP is the bus master, RD is an active-low output
that is asserted to read external memory on the data bus (D0–D23).
Otherwise, RD is tri-stated.
Write Enable—When the DSP is the bus master, WR is an active-low
output that is asserted to write external memory on the data bus (D0–D23).
Otherwise, the signals are tri-stated.
Transfer Acknowledge—If the DSP56362 is the bus master and there is
no external bus activity, or the DSP56362 is not the bus master, the TA input
is ignored. The TA input is a data transfer acknowledge (DTACK) function
that can extend an external bus cycle indefinitely. Any number of wait states
(1, 2. . .infinity) may be added to the wait states inserted by the BCR by
keeping TA deasserted. In typical operation, TA is deasserted at the start of
a bus cycle, is asserted to enable completion of the bus cycle, and is
deasserted before the next bus cycle. The current bus cycle completes one
clock period after TA is asserted synchronous to CLKOUT. The number of
wait states is determined by the TA input or by the bus control register
(BCR), whichever is longer. The BCR can be used to set the minimum
number of wait states in external bus cycles.
In order to use the TA functionality, the BCR must be programmed to at least
one wait state. A zero wait state access cannot be extended by TA
deassertion, otherwise improper operation may result. TA can operate
synchronously or asynchronously, depending on the setting of the TAS bit in
the operating mode register (OMR).
TA functionality may not be used while performing DRAM type accesses,
otherwise improper operation may result.
Signal Description
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