ADSP-21363KSWZ-1AA Analog Devices Inc, ADSP-21363KSWZ-1AA Datasheet - Page 35

IC DSP 32BIT 333MHZ EPAD 144LQFP

ADSP-21363KSWZ-1AA

Manufacturer Part Number
ADSP-21363KSWZ-1AA
Description
IC DSP 32BIT 333MHZ EPAD 144LQFP
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Fixed/Floating Pointr
Datasheet

Specifications of ADSP-21363KSWZ-1AA

Interface
DAI, SPI
Clock Rate
333MHz
Non-volatile Memory
ROM (512 kB)
On-chip Ram
384kB
Voltage - I/o
3.30V
Voltage - Core
1.20V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
144-LQFP Exposed Pad, 144-eLQFP, 144-HLQFP
No. Of Bits
32 / 40
Frequency
333MHz
Supply Voltage
1.2V
Supply Voltage Range
1.14V To 1.26V
Operating Temperature Range
0°C To +70°C
Digital Ic Case Style
QFP
No. Of Pins
144
Embedded Interface Type
SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADSP-21363KSWZ-1AA
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Sample Rate Converter—Serial Output Port
For the serial output port, the frame-sync is an input and should
meet setup and hold times with regard to the serial clock on the
output port. The serial data output has a hold time and delay
Table 32. SRC, Serial Output Port
1
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
The data, serial clock, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync can also come via PCG or SPORTs. PCG’s input can be
SRCSFS
SRCHFS
SRCTDD
SRCTDH
either CLKIN or any of the DAI pins.
1
1
1
1
Frame Sync Setup Before Serial Clock Rising Edge
Frame Sync Hold After Serial Clock Rising Edge
Transmit Data Delay After Serial Clock Falling Edge
Transmit Data Hold After Serial Clock Falling Edge
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
(SERIAL CLOCK)
(FRAME SYNC)
DAI_P20–1
DAI_P20–1
DAI_P20–1
(DATA)
t
SRCTDH
Rev. G | Page 35 of 56 | March 2011
Figure 28. SRC Serial Output Port Timing
t
SRCTDD
t
SRCCLKW
t
SRCSFS
SAMPLE EDGE
specification with regard to serial clock. Note that the serial
clock rising edge is the sampling edge and the falling edge is the
drive edge.
Min
3
3
2
t
SRCHFS
K and B Grade
t
SRCCLK
Max
10.5
Max
12.5
Y Grade
Unit
ns
ns
ns
ns

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