JD54LS164BCA National Semiconductor, JD54LS164BCA Datasheet - Page 98

• Manufacturer Part Number: JD54LS164BCA
• Manufacturer: National Semiconductor

Specifications of JD54LS164BCA

• Lead Free Status / Rohs Status: Not Compliant

NOTES:
Subgroup
Tc = 25 C
1/ Apply
2/ A = 2.5 V and B = 0.4 V.
3/ Output voltages shall be either:
4/ f
9 4/
10
11
shall be one-half of the input clock frequency. The input frequency on the "H" shall be one-half
of the clock input frequency and the "H" shall be shifted such that the "H" and
with the clock
MAX
a. H = 2.5 V minimum and L = 0.4 V maximum when using a high speed checker double comparator or,
b. H 1.5 V and L 1.5 V when using a high speed checker single comparator.
minimum limit specified is the frequency of the clock input pulse. The output frequency
f
t
t
t
f
t
t
t
Same tests, terminal conditions, and limits as subgroup 10, except T
MAX
PHL5
PLH1
PHL1
MAX
PHL5
PLH1
PHL1
Symbol
MIL-STD-
↓
method
fig. 12
3003
883
See
. Rise and fall times 6 ns. Input peak voltage 3 to 5 volts.
0 V
Same tests and terminal as subgroup 9, except T
Cases E,F
Cases 2,X
2.5 V minimum, 5.5 V maximum to clock input prior to test.
Test no.
76
77
78
79
Ser. in
1
2
A
2
3
Terminal conditions (pins not designated may be high
3
4
B
C
4
5
TABLE III. Group A inspection for device type 09- Continued.
C
= -55 C.
C
D
= 125 C.
5
7
INHB
GND
GND
GND
CLK
6
8
↓
a re coincident
CLK
IN
IN
IN
7
9
GND
GND
10
8
"
"
"
"
5.0 V
5.0 V
5.0 V
CLR
12
IN
9
2.0 V; or low
10
13
E
14
11
F
0.7 V; or open).
12
15
G
OUT
13
17
Q
"
"
"
"
H
14
18
IN
IN
IN
H
GND
GND
GND
Shift
load
15
19
5.0 V
V
16
20
"
"
"
"
CC
CLR to Q
CLR to Q
CLR to Q
Measured
CLK to Q
terminal
H
H
H
H
Min
Test Limits
25
20
5
5
5
5
"
"
"
Max
40
31
35
52
40
46
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns