AD5391BSTZ-5 Analog Devices Inc, AD5391BSTZ-5 Datasheet - Page 13

• Manufacturer Part Number: AD5391BSTZ-5
• Description: IC DAC 12BIT 16CHAN 3V 52LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD5391BSTZ-5

• Data Interface: I²C, Serial
• Design Resources: 8 to 16 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5390/1/2 (CN0029) AD5390/91/92 Channel Monitor Function (CN0030)
• Settling Time: 6µs
• Number Of Bits: 12
• Number Of Converters: 16
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 35mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Resolution (bits): 12bit
• Sampling Rate: 167kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analogue: 4.5V To 5.5V
• Supply Voltage Range - Digital: 2.7V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD5391EBZ - BOARD EVALUATION FOR AD5391
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TIMING CHARACTERISTICS: I
Guaranteed by design and characterization, not production tested. DV
All specifications T
Table 7.
Parameter
F
t
t
t
t
t
t
t
t
t
t
t
C
1
2
3
1
2
3
4
5
6
7
8
9
10
11
See F
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
to bridge the undefined region of SCL’s falling edge.
C
SCL
B
2
3
B
is the total capacitance of one bus line in pF; t
igure 6
.
1
SDA
SCL
MIN
Limit at T
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
300
0
300
20 + 0.1 C
400
to T
MAX
t
9
, unless otherwise noted.
MIN
B
CONDITION
START
, T
t
4
MAX
R
t
3
and t
2
F
C SERIAL INTERFACE
measured between 0.3 DV
Unit
kHz max
µs min
µs min
µs min
µs min
ns min
µs max
µs min
µs min
µs min
µs min
ns max
ns min
ns max
ns min
ns max
ns min
pF max
t
10
t
6
Figure 6. I
t
11
t
2
Rev. A | Page 13 of 44
2
Description
SCL clock frequency
SCL cycle time
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Capacitive load for each bus line
C Interface Timing Diagram
HIGH
LOW
HD
SU
HD
HD
SU
SU
BUF
F
R
F
F
F
F
, fall time of SDA when transmitting
, fall time of SDA when transmitting
, fall time of SDA when receiving (CMOS-compatible)
, fall time of SCL and SDA when receiving
, fall time of SCL and SDA when transmitting
, rise time of SCL and SDA when receiving (CMOS-compatible)
,
,
,
,
,
,
, bus free time between a stop and a start condition
DAT
STA
STO
, SCL low time
STA
DAT
DAT
, SCL high time
, start/repeated start condition hold time
, data setup time
setup time for repeated start
stop condition setup time
data hold time
data hold time
DD
DD
and 0.7 DV
t
5
= 2.7 V to 5.5 V; AV
t
7
IH
CONDITION
REPEATED
DD
MIN of the SCL signal)
START
.
t
4
DD
t
1
= 2.7 V to 5.5 V; AGND = DGND = 0 V.
AD5390/AD5391/AD5392
CONDITION
STOP
t
8