SC16C852LIB-F NXP Semiconductors, SC16C852LIB-F Datasheet - Page 44

SC16C852LIB-F

Manufacturer Part Number
SC16C852LIB-F
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SC16C852LIB-F

Number Of Channels
2
Transmitter And Receiver Fifo Counter
Yes
Data Rate
5Mbps
Package Type
LQFP
Mounting
Surface Mount
Pin Count
48
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Compliant
NXP Semiconductors
Table 40.
T
[1]
[2]
[3]
SC16C852L_3
Product data sheet
Symbol
t
t
t
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
N
WH
WL
w(clk)
XTAL1
su(A)
h(A)
su(RWL-CSL)
su(RWH-CSL)
d(stop-RXRDY)
d(start-TXRDY)
w(CS)
d(CS)
d(CS-Q)
dis(CS-QZ)
h(CS-RWH)
d(RW)
su(D-CSH)
h(CSH-D)
d(modem-IRQL)
d(CS-IRQH)R
d(stop-IRQL)
d(CS-RXRDYH)R
d(CS-TX)W
d(start-IRQL)
d(CS-IRQH)W
d(CS-TXRDYH)W
d(CS-Q)W
w(RESET_N)
amb
Applies to external clock, crystal oscillator max 24 MHz.
Maximum frequency =
RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.
= 40 C to +85 C; V
Dynamic characteristics - Motorola or 68 mode
Parameter
pulse width HIGH
pulse width LOW
clock pulse width
frequency on pin XTAL1
address setup time
address hold time
set-up time from R/W LOW to CS LOW
set-up time from R/W HIGH to CS LOW
delay time from stop to RXRDY
delay time from start to TXRDY
CS pulse width
CS delay time
delay time from CS to data output
disable time from CS to high-impedance
data output
hold time from CS to R/W HIGH
R/W delay time
set-up time from data input to CS HIGH
data input hold time after CS HIGH
delay time from modem to IRQ LOW
read delay time from CS to IRQ HIGH
delay time from stop to IRQ LOW
read delay time from CS to RXRDY HIGH
write delay time from CS to TX
delay time from start to IRQ LOW
write delay time from CS to IRQ HIGH
write delay time from CS to TXRDY HIGH
write delay time from CS to data output
pulse width on pin RESET
baud rate divisor
-------------- -
t
w clk
DD
1
= 1.65 V to 1.95 V; unless otherwise specified.
1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder
Rev. 03 — 18 January 2008
Conditions
25 pF load
25 pF load
25 pF load
25 pF load
[1][2]
[3]
[3]
[3]
[3]
[3]
Min
6
6
12.5
-
5
10
10
10
-
-
20
10
-
-
5
10
5
5
-
-
-
-
8T
-
-
-
-
10
1
RCLK
SC16C852L
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
© NXP B.V. 2008. All rights reserved.
Max
-
-
-
80
-
-
-
-
1T
8T
-
-
40
20
-
-
-
-
50
50
1T
50
24T
1T
50
50
50
-
(2
16
RCLK
RCLK
RCLK
RCLK
RCLK
1)
44 of 63
Unit
ns
ns
ns
MHz
ns
ns
ns
ns
s
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
ns
s
s
ns
ns
ns
ns

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