SC16C852LIB-F NXP Semiconductors, SC16C852LIB-F Datasheet
SC16C852LIB-F
Specifications of SC16C852LIB-F
Related parts for SC16C852LIB-F
SC16C852LIB-F Summary of contents
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SC16C852L 1.8 V dual UART, 5 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode bus interface Rev. 03 — 18 January 2008 1. General description The SC16C852L is a 1.8 V, low power, dual channel ...
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... Independent transmitter and receiver enable/disable I Pb-free, RoHS compliant packages offered 3. Ordering information Table 1. Type number SC16C852LIB SC16C852LIBS HVQFN32 plastic thermal enhanced very thin quad flat package; SC16C852LIET TFBGA36 SC16C852L_3 Product data sheet 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder Ordering information Package ...
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... NXP Semiconductors 4. Block diagram SC16C852L DATA BUS IOR IOW CONTROL RESET REGISTER CSA SELECT CSB POWER- LOWPWR CONTROL INTA, INTB INTERRUPT TXRDYA, TXRDYB CONTROL RXRDYA, RXRDYB Fig 1. Block diagram of SC16C852L (16 mode) SC16C852L_3 Product data sheet 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder ...
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... NXP Semiconductors SC16C852L DATA BUS R/W CONTROL RESET REGISTER SELECT CS POWER- LOWPWR CONTROL IRQ INTERRUPT TXRDYA, TXRDYB CONTROL RXRDYA, RXRDYB Fig 2. Block diagram of SC16C852L (68 mode) SC16C852L_3 Product data sheet 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder AND LOGIC LOGIC ...
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... V dual UART with 128-byte FIFOs and IrDA encoder/decoder terminal 1 index area RXB 3 4 SC16C852LIBS RXA (16 mode) TXA 5 TXB 6 7 CSA 8 CSB Transparent top view terminal 1 index area RXB 4 RXA SC16C852LIBS (68 mode) TXA 5 TXB Transparent top view Rev. 03 — 18 January 2008 SC16C852L 24 RESET 23 RTSA 22 INTA 21 INTB 002aac179 24 RESET ...
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... V dual UART with 128-byte FIFOs and IrDA encoder/decoder RXB 4 RXA 5 TXRDYB 6 SC16C852LIB (16 mode) 7 TXA TXB 8 OP2B 9 10 CSA 11 CSB LOWPWR RXB 4 5 RXA TXRDYB 6 SC16C852LIB (68 mode) TXA 7 TXB 8 9 OP2B LOWPWR Rev. 03 — 18 January 2008 SC16C852L 36 RESET 35 DTRB 34 DTRA 33 RTSA 32 OP2A 31 RXRDYA 30 INTA 29 INTB ...
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... NXP Semiconductors Fig 5. Pin configuration for TFBGA36 a. 16 mode b. 68 mode Fig 6. TFBGA36 ball mapping (transparent top view) SC16C852L_3 Product data sheet 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder ball A1 SC16C852LIET index area Transparent top view n. n. RXB ...
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... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin LQFP48 HVQFN32 TFBGA36 CDA 40 - CDB 16 - CSA/ CSB/ CTSA 38 25 CTSB 23 16 DSRA 39 - DSRB 20 - DTRA 34 - DTRB SC16C852L_3 Product data sheet 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder Type Description D5 I Address 0 select bit. Internal register address selection. ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin LQFP48 HVQFN32 TFBGA36 INTA/IRQ 30 22 INTB/n. IOR IOW/R OP2A 32 - OP2B 9 - RESET RESET RIA 41 - RIB 21 - RTSA 33 23 RTSB 22 15 SC16C852L_3 Product data sheet 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder Type Description ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin LQFP48 HVQFN32 TFBGA36 RXA 5 4 RXB 4 3 RXRDYA 31 - RXRDYB 18 - TXA 7 5 TXB 8 6 TXRDYA 43 - TXRDYB [ XTAL1 13 10 XTAL2 14 11 SC16C852L_3 Product data sheet 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder Type ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin LQFP48 HVQFN32 TFBGA36 LOWPWR 12 9 16/ n.c. 25 [1] HVQFN32 package die supply ground is connected to both V ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region ...
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... NXP Semiconductors The SC16C852L is capable of operation Mbit/s with an external 80 MHz clock. With a crystal, the SC16C852L is capable of operation up to 1.5 Mbit/s. The rich feature set of the SC16C852L is available through internal registers. These features are: selectable and programmable receive and transmit FIFO trigger levels, selectable TX and RX baud rates, and modem interface controls, and are all standard features ...
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... NXP Semiconductors 6.3 Internal registers The SC16C852L provides two sets of internal registers (A and B) consisting of 25 registers each for monitoring and controlling the functions of each channel of the UART. These registers are shown in Table General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LCR/LSR, SPR) ...
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... NXP Semiconductors 6.4 FIFO operation 6.4.1 32-byte FIFO mode When all four of these registers (TXINTLVL, RXINTLVL, FLWCNTH, FLWCNTL) in the ‘First extra feature register set’ are empty (0x00) the transmit and receive trigger levels are set by FCR[7:4]. In this mode the transmit and receive trigger levels are backward compatible to the SC16C652B (see transmit and receive data FIFOs are enabled by the FIFO Control Register bit 0 (FCR[0]) ...
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... NXP Semiconductors With the automatic hardware flow control function enabled, an interrupt is generated when the receive FIFO reaches the programmed trigger level. The RTSx (or DTRx) pin will not be forced to a logic 1 (RTS off), until the receive FIFO reaches the next trigger level. ...
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... NXP Semiconductors the receive FIFO passes the programmed trigger level. To clear this condition, the SC16C852L will transmit the programmed Xon1/Xon2 characters as soon as the number of characters in the receive FIFO drops below the programmed trigger level. 6.7 Special character detect A special character detect feature is provided to detect an 8-bit character when EFR[5] is set ...
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... NXP Semiconductors 6.9 Programmable baud rate generator The SC16C852L UART contains a programmable rational baud rate generator that takes any clock input and divides divisor in the range between 1 and (2 SC16C852L offers the capability of dividing the input frequency by rational divisor. The fractional part of the divisor is controlled by the CLKPRES register in the ‘first extra feature register set’ ...
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... NXP Semiconductors Fig 8. Crystal oscillator connection Fig 9. External clock connection Table 7. Output baud rate (bit/ 110 150 300 600 1.2 k 2.4 k 3.6 k 4.8 k 7.2 k 9.6 k 19.2 k 38.4 k 57.6 k 115.2 k SC16C852L_3 Product data sheet 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder ...
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... NXP Semiconductors 6.10 DMA operation The SC16C852L FIFO trigger level provides additional flexibility to the user for block mode operation. The user can optionally operate the transmit and receive FIFOs in the DMA mode (FCR[3]). The DMA mode affects the state of the RXRDYA/RXRDYB and TXRDYA/TXRDYB output pins ...
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... NXP Semiconductors SC16C852L DATA BUS AND IOR CONTROL IOW LOGIC RESET REGISTER CSA SELECT CSB LOGIC POWER- LOWPWR DOWN CONTROL INTA, INTB INTERRUPT TXRDYA, TXRDYB CONTROL RXRDYA, RXRDYB LOGIC Fig 10. Internal Loopback mode diagram SC16C852L_3 Product data sheet 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder ...
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... NXP Semiconductors 6.12 Sleep mode Sleep mode is an enhanced feature of the SC16C852L UART enabled when EFR[4], the enhanced functions bit, is set and when IER[4] of both channels are set. 6.12.1 Conditions to enter Sleep mode Sleep mode is entered when: • Modem input pins are not toggling. ...
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... NXP Semiconductors 6.14 RS-485 features 6.14.1 Auto RS-485 RTS control Normally the RTSA/RTSB pin is controlled by MCR bit hardware flow control is enabled, the logic state of the RTSx pin is controlled by the hardware flow control circuitry. AFCR2 register bit 4 will take the precedence over the other two modes; once this bit is set, the transmitter will control the state of the RTSx pin ...
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... NXP Semiconductors 6.14.3.2 Auto address detection If Special Character Detect is enabled (EFR[5] is set and the Xoff2 register contains the address byte) the receiver will try to detect an address byte that matches the programmed character in the Xoff2 register. If the received byte is a data byte or an address byte that does not match the programmed character in the Xoff2 register, the receiver will discard these data ...
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Table 10. SC16C852L internal registers [ Register Default Bit 7 [2] General register set RHR XX bit THR XX bit IER 00 CTS [3] interrupt 0 ...
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Table 10. SC16C852L internal registers …continued [ Register Default Bit 7 [5] Enhanced feature register set EFR 00 Auto CTS Xon1 00 bit Xon2 00 bit 15 ...
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... NXP Semiconductors 7.1 Transmit (THR) and Receive (RHR) Holding Registers The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (D7 to D0) to the transmit FIFO. The THR empty fl ...
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... NXP Semiconductors Table 11. Bit Symbol Description 1 IER[1] 0 IER[0] 7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation When the receive FIFO is enabled (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are enabled, the receive interrupts and register status will reflect the following: • ...
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... NXP Semiconductors 7.3 FIFO Control Register (FCR) This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger levels, and select the DMA mode. 7.3.1 DMA mode 7.3.1.1 Mode 0 (FCR bit this mode, Transmit Ready (TXRDY) will logic 0 whenever the FIFO (THR, if FIFO is not enabled) is empty ...
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... NXP Semiconductors Table 12. Bit 3 (cont [1] For 128-byte FIFO mode, refer to [2] For 128-byte FIFO mode, refer to Table 13. FCR[ [1] When RXINTLVL, TXINTLVL, FLWCNTL or FLWCNTH contains any value other than 0x00, receive and transmit trigger levels are set by RXINTLVL, TXINTLVL registers (see Table 14. ...
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... NXP Semiconductors 7.4 Interrupt Status Register (ISR) The SC16C852L provides six levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced ...
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... NXP Semiconductors 7.5 Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. Table 17. Bit 7 6 5:3 2 1:0 Table 18 ...
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... NXP Semiconductors 7.6 Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. Table 21. Bit SC16C852L_3 Product data sheet 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder Modem Control Register bits description Symbol Description MCR[7] ...
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... NXP Semiconductors 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C852L and the CPU. Table 22. Bit Symbol 7 LSR[7] 6 LSR[6] 5 LSR[5] 4 LSR[4] 3 LSR[3] 2 LSR[2] 1 LSR[1] 0 LSR[0] SC16C852L_3 Product data sheet 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder ...
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... NXP Semiconductors 7.8 Modem Status Register (MSR) This register shares the same address as EFCR register. This is a read-only register and it provides the current state of the control interface signals from the modem, or other peripheral device to which the SC16C852L is connected. Four bits of this register are used to indicate the changed information ...
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... NXP Semiconductors 7.9 Extra Feature Control Register (EFCR) This is a write-only register, and it allows the software access to these registers: first extra feature register set, second extra feature register set, Transmit FIFO Level Counter (TXLVLCNT), and Receive FIFO Level Counter (RXLVLCNT). Table 24. ...
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... NXP Semiconductors 7.14 Enhanced Feature Register (EFR) Enhanced features are enabled or disabled using this register. Bits 0 through 4 provide single or dual character software flow control selection. When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words are concatenated into two sequential numbers ...
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... NXP Semiconductors Table 26. Cont [1] When using a software flow control the Xon/Xoff characters cannot be used for data transfer. 7.15 Transmit Interrupt Level register (TXINTLVL) This 8-bit register is used to store the transmit FIFO trigger levels used for DMA and interrupt generation. Trigger levels from 1 to 128 can be programmed with a granularity of 1 ...
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... NXP Semiconductors [1] For 32-byte FIFO mode, refer to 7.17 Flow Control Trigger Level High (FLWCNTH) This 8-bit register is used to store the receive FIFO high threshold levels to start/stop transmission during hardware/software flow control. bit settings; see Table 29. Bit 7:0 [1] For 32-byte FIFO mode, refer to 7 ...
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... NXP Semiconductors 7.20 RS-485 turn-around time delay (RS485TIME) The value in this register controls the turn-around time of the external line transceiver in bit time. In automatic 9-bit mode RTSA/RTSB or DTRA/DTRB pin is used to control the direction of the line driver, after the last bit of data has been shifted out of the transmit shift register the UART will count down the value in this register ...
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... NXP Semiconductors 7.22 Advanced Feature Control Register 1 (AFCR1) Table 34. Bit 7 6 [1] It takes 4 XTAL1 clocks to reset the device. SC16C852L_3 Product data sheet 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder Advanced Feature Control Register 1 register bits description Symbol Description AFCR1[7] Concurrent write ...
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... NXP Semiconductors 7.23 SC16C852L external reset condition and software reset These two reset methods are identical and will reset the internal registers as indicated in Table 35. Table 35. Register IER FCR ISR LCR MCR LSR MSR EFCR SPR DLL DLM TXLVLCNT RXLVLCNT EFR Xon1 ...
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... NXP Semiconductors 8. Limiting values Table 37. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol amb T stg P /pack tot [1] V should not exceed 2 Static characteristics Table 38 + amb Symbol V IL(clk) V IH(clk LIL I LIH I L(clk DD(sleep) I DD(lp [1] Except XTAL2. [2] Sleep current might be higher if there is any activity on the UART data bus during Sleep mode. ...
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... NXP Semiconductors 10. Dynamic characteristics Table 39. Dynamic characteristics - Intel or 16 mode + 1. 1.95 V; unless otherwise specified. amb DD Symbol Parameter t pulse width HIGH WH t pulse width LOW WL t clock pulse width w(clk) f frequency on pin XTAL1 XTAL1 t address setup time su(A) t address hold time ...
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... NXP Semiconductors Table 40. Dynamic characteristics - Motorola or 68 mode + 1. 1.95 V; unless otherwise specified. amb DD Symbol Parameter t pulse width HIGH WH t pulse width LOW WL t clock pulse width w(clk) f frequency on pin XTAL1 XTAL1 t address setup time su(A) t address hold time h(A) t set-up time from R/W LOW to CS LOW ...
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... NXP Semiconductors 10.1 Timing diagrams su(A) CSx t d(CSL-IOWL) IOW Fig 11. General write timing in 16 mode su( su(RWL-CSL) R Fig 12. General write timing in 68 mode SC16C852L_3 Product data sheet 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder t h(A) valid address t h(IOW-CS) active t t w(IOW) ...
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... NXP Semiconductors su(A) CSx t d(CS-IOR) IOR Fig 13. General read timing in 16 mode su( su(RWH-CSL) R Fig 14. General read timing in 68 mode external clock -------------- - XTAL1 t w clk Fig 15. External clock timing SC16C852L_3 Product data sheet 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder ...
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... NXP Semiconductors IOW RTSA, RTSB change of state DTRA, DTRB CDA, CDB CTSA, CTSB DSRA, DSRB INT IOR RIA, RIB Fig 16. Modem input/output timing in 16 mode (1) CS (write) RTSA, RTSB change of state DTRA, DTRB CDA, CDB CTSA, CTSB DSRA, DSRB IRQ (2) CS (read) RIA, RIB (1) CS timing during a write cycle ...
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... NXP Semiconductors RXA, RXB (1)(2) INT IOR (1) INT is active when RX FIFO fills up to trigger level or a time-out condition happens (see (2) INT is cleared when RX FIFO drops below trigger level. Fig 18. Receive timing in 16 mode RXA, RXB (1)(2) IRQ CS (read) (1) IRQ is active when RX FIFO fills up to trigger level or time-out condition happens (see (2) IRQ is cleared when RX FIFO drops below trigger level ...
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... NXP Semiconductors RXA, RXB RXRDYA, RXRDYB IOR Fig 20. Receive ready timing in non-FIFO mode (16 mode) RXA, RXB RXRDYA, RXRDYB CS (read) Fig 21. Receive ready timing in non-FIFO mode (68 mode) SC16C852L_3 Product data sheet 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder start bit ...
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... NXP Semiconductors RXA, RXB RXRDYA, RXRDYB IOR Fig 22. Receive ready timing in FIFO mode (16 mode) RXA, RXB RXRDYA, RXRDYB CS (read) Fig 23. Receive ready timing in FIFO mode (68 mode) SC16C852L_3 Product data sheet 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder start bit ...
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... NXP Semiconductors TXA, TXB (1)(2) INT active IOW (1) INT is active when TX FIFO is empty or TX FIFO drops below trigger level. (2) INT is cleared when ISR is read or TX FIFO fills up to trigger level. Fig 24. Transmit timing in 16 mode TXA, TXB (1)(2) IRQ t d(CS-TX)W active CS (write) (1) IRQ is active when TX FIFO is empty or TX FIFO drops below trigger level ...
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... NXP Semiconductors TXA, TXB IOW active byte #1 t d(IOW-TXRDYH) TXRDYA, TXRDYB Fig 26. Transmit ready timing in non-FIFO mode (16 mode) TXA, TXB active CS (write byte #1 TXRDYA, TXRDYB Fig 27. Transmit ready timing in non-FIFO mode (68 mode) SC16C852L_3 Product data sheet 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder ...
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... NXP Semiconductors TXA, TXB IOW active byte # byte #128 TXRDYA, TXRDYB Fig 28. Transmit ready timing in FIFO mode (DMA mode ‘1’ mode TXA, TXB CS (write) active byte # byte #128 TXRDYA, TXRDYB Fig 29. Transmit ready timing in FIFO mode (DMA mode ‘1’ mode ...
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... NXP Semiconductors TX data IrDA TX data Fig 30. Infrared transmit timing IrDA RX data RX data Fig 31. Infrared receive timing SC16C852L_3 Product data sheet 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder UART frame start bit time bit time start Rev. 03 — 18 January 2008 ...
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... NXP Semiconductors 11. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...
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... NXP Semiconductors HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 0.85 mm terminal 1 index area terminal 1 index area 32 DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors TFBGA36: plastic thin fine-pitch ball grid array package; 36 balls; body 3.5 x 3.5 x 0.8 mm ball A1 index area 1 ball A1 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.25 0.90 0.35 mm 1.15 0.15 0.75 0.25 OUTLINE VERSION IEC - - - SOT912-1 Fig 34. Package outline SOT912-1 (TFBGA36) ...
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... NXP Semiconductors 12. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 12.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 12.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 35. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 13. Abbreviations Table 43. Acronym CPU DLL DLM DMA FIFO IrDA ISDN LSB MSB PCB RoHS ...
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... NXP Semiconductors 14. Revision history Table 44. Revision history Document ID Release date SC16C852L_3 20080118 • Modifications: added TFBGA36 package option • Table 10 “SC16C852L internal – TXLVLCNT changed from “R/W” to “R” – RXLVLCNT changed from “R/W” to “R” • Section 7.12 “Transmit FIFO Level Count number of characters available ...” ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 Functional description . . . . . . . . . . . . . . . . . . 11 6.1 UART A-B functions . . . . . . . . . . . . . . . . . . . . 12 6.2 Extended mode (128-byte FIFO 6.3 Internal registers 6.4 FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 14 6.4.1 32-byte FIFO mode ...