SC1200UCL-266 AMD (ADVANCED MICRO DEVICES), SC1200UCL-266 Datasheet - Page 76

• Manufacturer Part Number: SC1200UCL-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UCL-266

• Lead Free Status / Rohs Status: Not Compliant

76
Offset 34h-37h
Power-on reset value: The BOOT16 strap pin selects "Enable 16-Bit Wide Boot Memory".
28:20
Bit
12
11
10
31
30
29
9
8
7
6
5
4
3
2
1
0
Table 4-2. Pin Multiplexing, Interrupt Selection, and Base Address Registers (Continued)
Description
TRDESEL (Select TRDE#). Selects ball function.
Ball #
H1 / D11
EIDE (Enable IDE Outputs). This bit enables IDE output signals.
0: IDE signals are HiZ. Other signals multiplexed on the same balls are HiZ until this bit is set. (without regard to bit 24 of
1: Signals are enabled.
ETFT (Enable TFT Outputs). This bit enables TFT output signals, that are multiplexed with the Parallel Port and controlled
by PMR[23].
0: Signals TFTD[17:0], TFTDE and TFTDCK are set to 0.
1: Signals TFTD[17:0], TFTDE and TFTDCK are enabled.
Note:
IOCHRDY (Select IOCHRDY). Selects ball function.
Ball #
H4 / C9
IDE1SEL (Select IDE Channel 1). Selects IDE Channel 1 or GPIO ball functions. Works in conjunction with PMR[18] and
PMR[17], see PMR[18] and PMR[17] for definitions.
DOCCSSEL (Select DOCCS#). Selects DOCCS# or GPIO20 ball functions. Works in conjunction with PMR[23], see
PMR[23] for definition.
SP3SEL (Select UART3). Selects ball functions.
Ball #
J28 / AK8
J3 / C11
IOCS0SEL (Select IOCS0#). Selects ball function. Works in conjunction with PMR[23], see PMR[23] for definition.
INTCSEL (Select INTC#). Selects ball function. Works in conjunction with PMR[9], see PMR[9] for definition.
Reserved. Write as read.
DOCWRSEL (Select DiskOnChip and NAND Flash Command Lines). Selects ball functions. Works in conjunction with
PMR[21], see PMR[21] for definition.
Reserved. Write as read.
PCBEEPSEL (Select PC_BEEP). Selects ball function.
Ball #
AL15 / V31
DID0 (Ball C5) Strap Status. (Read Only) Represents the value of the strap that is latched after power-on reset. Read in
conjunction with bit 29.
FPCI_MON (Ball A4) Strap Status. (Read Only) Represents the value of the strap that is latched after power-on reset.
Indicates if Fast-PCI monitoring output signals (instead of Parallel Port and some audio signals) are enabled. The state of
this bit along with PMR[27] control the Fast-PCI monitoring function. See PMR[27] definition.
DID1 (Ball C6) Strap Status. (Read Only) Represents the value of the strap that is latched after power-on reset. Read in
conjunction with bit 31.
Reserved.
this register). This bit does not control IDE channel 1 control signals selected by bit 8 of this register.
TFTDCK that is multiplexed on IDE_RST# (ball AA1) is also enabled by this bit.
32579B
0: Sub-ISA Signal
Name
TRDE#
0: PCI, GPIO Signal
Name
GPIO19
INTC#
0: IR Signals
Name
IRRX1
IRTX
0: GPIO Signal
Name
GPIO16
F_DEVSEL#
Miscellaneous Configuration Register - MCR (R/W)
Add’l Dependencies
None
Add’l Dependencies
PMR[4] = 0
Add’l Dependencies
None
None
Add’l Dependencies
FPCI_MON = 0
FPCI_MON = 1
PMR[4] = 1
AMD Geode™ SC1200/SC1201 Processor Data Book
1: GPIO Signal
Name
GPIO0
1: Sub-ISA Signal
Name
IOCHRDY
Undefined
1: Serial Port Signals
Name
SIN3
SOUT3
1: Audio Signal
Name
PC_BEEP
F_DEVSEL#
Add’l Dependencies
None
Add’l Dependencies
PMR[4] = 1
PMR[4] = 0
Add’l Dependencies
None
None
Add’l Dependencies
FPCI_MON] = 0
FPCI_MON = 1
General Configuration Block
Reset Value: 0000001h