SC1200UCL-266 AMD (ADVANCED MICRO DEVICES), SC1200UCL-266 Datasheet - Page 356

• Manufacturer Part Number: SC1200UCL-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UCL-266

• Lead Free Status / Rohs Status: Not Compliant

356
Offset C08h-C0Bh
Offset C0Ch-C0Fh
Offset C10h-C13h
Offset C14h-C17h
31:25
24:16
15:10
31:25
24:16
31:5
31:0
Bit
4:3
2:1
9:0
0
Table 7-9. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)
Description
Reserved.
TV DAC Mode Bits [1:0]. Determines signal order of the TV DAC outputs. Used in conjunction with TV DAC Mode Bit 2
(F4BAR0+Memory Offset C04h[30]).
SyncMode. Determines where sync is output in SCART mode.
00: Reserved.
01: Sync is added to TVG.
10: Sync is output on the CVBS signal.
11: Reserved.
CS (Component Setup).
0: No setup is applied.
1: A 7.5 IRE setup is applied to the YCbCr output.
SCFREQ (Subcarrier Frequency). Defines the subcarrier frequency.
The value programmed is: round(fsc/fclk x 2
where fsc is the desired subcarrier frequency, and fclk is the clock frequency (27 MHz).
Reserved.
VSTART (Vertical Start). Defines the vertical start position of the top field, relative to the start of VSYNC (line 1 for PAL, line
4 for NTSC).
For 480-line NTSC this field is set to 18 (12h).
For 576-line PAL this field is set to 22 (16h).
Reserved.
HSTART (Horizontal Start). Defines the start of active video relative to the start of the line (hcount = 0) in 13.5 MHz clock
periods. The number programmed is START − 9.
For example:
NTSC:
PAL:
Reserved.
DISPHEIGHT (Display Height). Defines the height of a displayed field in lines. Programmed value equals LINE − 1.
For 720x480 NTSC, set to 239 (EFh).
For 720x576 PAL, set to 287 (11Fh).
C04h[30]
x
0
0
1
1
TV DAC Mode Bits [2:0]
Active video starts a nominal 122 13.5 MHz clock periods after the start of line.
The number programmed is 113 (71h).
Active video starts 132 13.5 MHz clock periods after the start of line.
The number programmed is 123 (7Bh).
32579B
C08h[4]
x
0
1
0
1
C08h[3]
0
1
1
1
1
Timing & Encoder Control 3 Register
Subcarrier Frequency Register
Display Position Register
Display Size Register
CVBS
CVBS
CVBS
TVB
D24
32)
Cr
Video Processor Module - Video Processor Registers - Function 4
CVBS
CVBS
SVY
TVR
A24
Cb
Ball No.
AMD Geode™ SC1200/SC1201 Processor Data Book
SVC
TVB
TVR
C23
Cb
Cr
CVBS
Reset Value: 00EF02CFh
Reset Value: 21F07C1Fh
TVG
TVG
A23
Reset Value: 00000000h
Reset Value: 00120071h
Y
Y
Mode
Super Video
SCART
SCART
YCbCr
YCbCr