SC1200UCL-266 AMD (ADVANCED MICRO DEVICES), SC1200UCL-266 Datasheet - Page 148

• Manufacturer Part Number: SC1200UCL-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UCL-266

• Lead Free Status / Rohs Status: Not Compliant

6.2.5.1
The ISA bus controller issues multiple ISA cycles to satisfy
PCI transactions that are larger than 16 bits. A full 32-bit
read or write results in two 16-bit ISA transactions or four 8-
bit ISA transactions. The ISA controller gathers the data
from multiple ISA read cycles and returns TRDY# to the
PCI bus.
SA[23:0] are a concatenation of ISA LA[23:17] and
SA[19:0] and perform equivalent functionality at a reduced
pin count.
Figure 6-2 shows the relationship between a PCI cycle and
the corresponding ISA cycle generated.
148
RD#,WR#,IOR#,IOW#
MEMR#,MEMW#
AD[31:0] (Read)
AD[31:0] (Write)
Fast-PCI_CLK
Sub-ISA Bus Cycles
FRAME#
ISACLK
TRDY#
STOP#
IRDY#
BALE
32579B
Figure 6-2. Non-Posted Fast-PCI to ISA Access
Note: Not all signals described in Figure 6-2 are available
6.2.5.2
Multiple PCI cycles occur for every slower ISA cycle. This
prevents slow PCI cycles from occupying too much band-
width and allows access to other PCI traffic. Figure 6-3 on
page 149 shows the relationship of PCI cycles to an ISA
cycle with PCI delayed transactions enabled.
externally. See Section 3.4.8 "Sub-ISA Interface
Signals" on page 59 for more information about
which Sub-ISA signals are externally available on
the SC1200/SC1201 processor.
AMD Geode™ SC1200/SC1201 Processor Data Book
Sub-ISA Support of Delayed PCI Transactions
Core Logic Module