SC1200UCL-266 AMD (ADVANCED MICRO DEVICES), SC1200UCL-266 Datasheet - Page 180

• Manufacturer Part Number: SC1200UCL-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UCL-266

• Lead Free Status / Rohs Status: Not Compliant

180
00h-01h
02h-03h
04h-05h
06h-07h
08h
09h-0Bh
0Ch
0Dh
0Eh
0Fh
10h-13h
14h-2Bh
2Ch-2Dh
2Eh-2Fh
30h-3Fh
40h-43h
44h-FFh
00h-01h
02h-03h
04h-05h
06h-07h
08h-09h
0Ah-1Bh
1Ch-1Fh
20h-21h
22h-23h
24h-27h
28h-4Fh
50h-FFh
F1BAR0+
I/O Offset
F1 Index
Table 6-17. F1: PCI Header Registers for SMI Status and ACPI Support Summary
Width
Width
(Bits)
(Bits)
16
16
16
16
24
32
---
16
16
---
32
---
16
16
16
16
16
---
32
16
16
32
---
---
8
8
8
8
8
32579B
Read to
RO/RC
Enable
Type
Type
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RC
RO
RO
RC
---
---
---
---
---
---
Table 6-18. F1BAR0: SMI Status Registers Summary
Name
Vendor Identification Register
Device Identification Register
PCI Command Register
PCI Status Register
Device Revision ID Register
PCI Class Code Register
PCI Cache Line Size Register
PCI Latency Timer Register
PCI Header Type Register
PCI BIST Register
Base Address Register 0 (F1BAR0) — Sets the base address for
the I/O mapped SMI Status Registers (summarized in Table 6-18).
Reserved
Subsystem Vendor ID
Subsystem ID
Reserved
Base Address Register 1 (F1BAR1) — Sets the base address for
the I/O mapped ACPI Support Registers (summarized in Table 6-
19)
Reserved
Name
Top Level PME/SMI Status Mirror Register
Top Level PME/SMI Status Register
Second Level General Traps & Timers PME/SMI Status Mirror
Register
Second Level General Traps & Timers PME/SMI Status Register
SMI Speedup Disable Register
Reserved
ACPI Timer Register
Second Level ACPI PME/SMI Status Mirror Register
Second Level ACPI PME/SMI Status Register
External SMI Register
Not Used
The I/O mapped registers located here (F1BAR0+I/O Offset 50h-FFh) are also accessible at F0
Index 50h-FFh. The preferred method is to program these registers through the F0 register space.
AMD Geode™ SC1200/SC1201 Processor Data Book
Core Logic Module - Register Summary
00000001h
00000001h
00000000h
xxxxxxxxh
068000h
100Bh
100Bh
0501h
0000h
0280h
0501h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
Reset
Value
Reset
Value
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
(Table 6-32)
(Table 6-33)
Reference
Reference
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