AD670JN Analog Devices Inc, AD670JN Datasheet - Page 4

• Manufacturer Part Number: AD670JN
• Description: IC ADC 8BIT SGNL COND 20-DIP
• Manufacturer: Analog Devices Inc

Specifications of AD670JN

• Rohs Status: RoHS non-compliant
• Number Of Bits: 8
• Sampling Rate (per Second): 10k
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 450mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 20-DIP (0.300", 7.62mm)

AD670
CIRCUIT OPERATION/FUNCTIONAL DESCRIPTION
The AD670 is a functionally complete 8-bit signal conditioning
A/D converter with microprocessor compatibility. The input
section uses an instrumentation amplifier to accomplish the
voltage to current conversion. This front end provides a high
impedance, low bias current differential amplifier. The com-
mon-mode range allows the user to directly interface the device
to a variety of transducers.
The AID conversions are controlled by R/W, CS, and CE. The
R/W line directs the converter to read or start a conversion. A
minimum write/start pulse of 300 ns is required on either CE or
CS. The STATUS line goes high, indicating that a conversion is
in process. The conversion thus begun, the internal 8-bit DAC
is sequenced from MSB to LSB using a novel successive ap-
proximation technique. In conventional designs, the DAC is
stepped through the bits by a clock. This can be thought of as a
static design since the speed at which the DAC is sequenced is
determined solely by the clock. No clock is used in the AD670.
Instead, a “dynamic SAR” is created consisting of a string of in-
verters with taps along the delay line. Sections of the delay line
between taps act as one shots. The pulses are used to set and re-
set the DAC’s bits and strobe the comparator. When strobed,
the comparator then determines whether the addition of each
successively weighted bit current causes the DAC current sum
to be greater or less than the input current. If the sum is less,
the bit is turned off. After all bits are tested, the SAR holds an
8-bit code representing the input signal to within 1/2 LSB
Figure 1. AD670 Block Diagram and Terminal
Configuration (AII Packages)
Model
AD670JN
AD670JP
AD670KN
AD670KP
AD670AD
AD670BD
AD670SD
NOTES
1
2
For details on grade and package offerings screened in accordance with MIL-STD-883 refer to the Analog Devices
Military Products Databook.
D = Ceramic DIP; N = Plastic DIP; P = Plastic Leaded Chip Carrier.
1
Temperature
Range
0 C to +70 C
0 C to +70 C
0 C to +70 C
0 C to +70 C
–40 C to +85 C
–40 C to +85 C
–55 C to +125 C
Relative Accuracy
@ +25 C
1/2 LSB
1/2 LSB
1/4 LSB
1/4 LSB
1/2 LSB
1/4 LSB
1/2 LSB
ORDERING GUIDE
–4–
ABSOLUTE MAXIMUM RATINGS*
V
Digital Inputs (Pins 11–15) . . . . . . . . . . . –0.5 V to V
Digital Outputs (Pins 1–9) . Momentary Short to V
Analog Inputs (Pins 16–19) . . . . . . . . . . . . . . . –30 V to +30 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW
Storage Temperature Range . . . . . . . . . . . . . –65 C to +150 C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300 C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
accuracy. Ease of implementation and reduced dependence on
process related variables make this an attractive approach to a
successive approximation design.
The SAR provides an end-of-conversion signal to the control
logic which then brings the STATUS line low. Data outputs re-
main in a high impedance state until R/W is brought high with
CE and CS low and allows the converter to be read. Bringing
CE or CS high during the valid data period ends the read cycle.
The output buffers cannot be enabled during a conversion. Any
convert start commands will be ignored until the conversion
cycle is completed; once a conversion cycle has been started it
cannot be stopped or restarted.
The AD670 provides the user with a great deal of flexibility by
offering two input spans and formats and a choice of output
codes. Input format and input range can each be selected. The
BPO/UPO pin controls a switch which injects a bipolar offset
current of a value equal to the MSB less 1/2 LSB into the sum-
ming node of the comparator to offset the DAC output. Two
precision 10 to 1 attenuators are included on board to provide
input range selection of 0 V to 2.55 V or 0 mV to 255 mV. Ad-
ditional ranges of –1.28 V to 1.27 V and –128 mV to 127 mV
are possible if the BPO/UPO switch is high when the conversion
is started. Finally, output coding can be chosen using the FOR-
MAT pin when the conversion is started. In the bipolar mode
and with a Logic 1 on FORMAT, the output is in two’s comple-
ment; with a Logic 0, the output is offset binary.
permanent damage to the device. This is a stress rating only and functional
operation of the device at them or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CC
to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +7.5 V
Gain Accuracy
@ +25 C
1.5 LSB
1.5 LSB
0.75 LSB
0.75 LSB
1.5 LSB
0.75 LSB
1.5 LSB
Package Option
Plastic DIP (N-20)
PLCC (P-20A)
Plastic DIP (N-20)
PLCC (P-20A)
Ceramic DIP (D-20)
Ceramic DIP (D-20)
Ceramic DIP (D-20)
2
CC
or Ground
CC
REV. A
+0.5 V