LTC2424IG Linear Technology, LTC2424IG Datasheet - Page 10

• Manufacturer Part Number: LTC2424IG
• Description: IC ADC 20BIT 4CH MICROPWR 28SSOP
• Manufacturer: Linear Technology

Specifications of LTC2424IG

• Number Of Bits: 20
• Sampling Rate (per Second): 7.5
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP (0.200", 5.30mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PIN
LTC2424/LTC2428
CSADC (Pin 23): ADC Chip Select Input. A low on this pin
enables the SDO digital output and following each conver-
sion, the ADC automatically enters the Sleep mode and
remains in a low power state as long as CSADC is high. If
CSADC is low during the sleep state, the device draws
normal power. A high on this pin also disables the SDO
digital output. A low-to-high transition on CSADC during
the Data Output state aborts the data transfer and starts a
new conversion. For normal operation, drive this pin in
parallel with CSMUX.
SDO (Pin 24): Three-State Digital Output. During the data
output period this pin is used for serial data output. When
the chip select CSADC is high (CSADC = V
is in a high impedance state. During the Conversion and
Sleep periods, this pin can be used as a conversion status
output. The conversion status can be observed by pulling
CSADC low.
FU CTIO AL BLOCK DIAGRA
TEST CIRCUITS
10
FS
U
ZS
U
GND
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
V
SET
SET
CC
FUNCTIONS
U
U
SDO
U
Hi-Z TO V
V
V
3.4k
OL
OH
TO V
TO Hi-Z
OH
OH
DAC
C
LOAD
24248 TC01
= 20pF
CC
), the SDO pin
W
SCK (Pin 25): Shift Clock for Data Out. This clock synchro-
nizes the serial data transfer of the ADC data output. Data
is shifted out of SDO on the falling edge of SCK. For normal
operation, drive this pin in parallel with CLK.
F
frequencies and conversion time. When the F
connected to V
oscillator and the digital filter first null is located at 50Hz.
When the F
converter uses its internal oscillator and the digital filter
first null is located at 60Hz. When F
external clock signal with a frequency f
uses this signal as its clock and the digital filter first null is
located at a frequency f
word rate is f
O
(Pin 26): Digital input which controls the ADC’s notch
ADC
O
EOSC
CC
pin is connected to GND (F
(F
/20510.
O
AUTOCALIBRATION
DECIMATING FIR
= V
SDO
AND CONTROL
CC
EOSC
Hi-Z TO V
V
V
OH
OL
), the converter uses its internal
V
TO Hi-Z
TO V
CC
/2560. The resulting output
3.4k
OL
C
OL
LOAD
24248 TC02
= 20pF
OSCILLATOR
INTERFACE
INTERNAL
CHANNEL
SELECT
SERIAL
EOSC
O
is driven by an
, the converter
O
24248 BD
= OV), the
(INT/EXT)
O
F
SDO
SCK
CSADC
CSMUX
D
CLK
pin is
O
IN