MAX1396ETB+T Maxim Integrated Products, MAX1396ETB+T Datasheet - Page 8

• Manufacturer Part Number: MAX1396ETB+T
• Description: IC ADC 12BIT 312.5KSPS 10-TDFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX1396ETB+T

• Number Of Bits: 12
• Sampling Rate (per Second): 312.5k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 830µW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-WFDFN Exposed Pad
• Number Of Adc Inputs: 2
• Architecture: SAR
• Conversion Rate: 312 KSPs
• Resolution: 12 bit
• Interface Type: Serial
• Voltage Reference: External
• Supply Voltage (max): 3.3 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MAX1396ETB+T

1.5V to 3.6V, 312.5ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 12-Bit, SAR ADCs
The MAX1393/MAX1396 use an input track and hold
(T/H) circuit along with a SAR to convert an analog input
signal to a serial 12-bit digital output data stream. The
serial interface provides easy interfacing to microproces-
sors and DSPs. Figure 3 shows the simplified functional
diagram for the MAX1393 (1 channel, true differential)
and the MAX1396 (2 channels, single ended).
The equivalent input circuit of Figure 4 shows the
MAX1393/MAX1396 input architecture, which is com-
posed of a T/H, a comparator, and a switched-capacitor
DAC. The T/H enters its tracking mode on the falling
edge of CS (while OE is held low). The positive input
capacitor is connected to AIN+ (MAX1393), or to AIN1 or
AIN2 (MAX1396). The negative input capacitor is con-
nected to AIN- (MAX1393) or GND (MAX1396). The T/H
enters its hold mode on the 3rd falling edge of SCLK
8
MAX1393 MAX1396
_______________________________________________________________________________________
10
—
—
—
—
1
2
3
4
5
6
7
8
9
PIN
True-Differential Analog Input T/H
—
—
—
10
—
1
2
3
4
5
6
7
8
9
Detailed Description
UNI/
NAME
DOUT
SCLK
AIN+
AIN2
AIN1
GND
AIN-
V
REF
EP
DD
/CH2
Positive Supply Voltage. Connect V
with a 0.1μF capacitor as close to the device as possible.
Negative Analog Input
Analog Input Channel 2
Positive Analog Input
Analog Input Channel 1
Ground
External Reference Voltage Input. V
0.1μF capacitor as close to the device as possible.
Input-Mode Select. Drive UNI/
select bipolar input mode. In unipolar mode, the output data is in straight binary format. In
bipolar mode, the output data is in two’s complement format.
Channel-Select Input. Pull
channel 2.
Active-Low Output Enable. Pull
Connect to
with DSP devices.
Active-Low Chip-Select Input. A falling edge on
Serial-Data Output. DOUT changes state on the falling edge of SCLK. DOUT is high
impedance when
Serial-Clock Input. SCLK drives the conversion process and clocks data out. Acquisition
ends on the 3rd falling edge after the
15th falling edge and the device enters AutoShutdown mode (see Figures 8, 9, and 10).
Exposed Pad. Not internally connected. Connect the exposed pad to GND or leave unconnected.
to interface with SPI, QSPI, and MICROWIRE devices or set low to interface
is high.
/CH2 low to select channel 1. Drive
Figure 3. Simplified Functional Diagram
AIN+ (AIN1)*
AIN- (AIN2)*
*INDICATES THE MAX1396
high to select unipolar input mode. Pull UNI/
low to enable DOUT. Drive
DD
REF
to a 1.5V to 3.6V power supply. Bypass V
REF
= 0.6V to (V
FUNCTION
falling edge. The LSB is clocked out on the SCLK
AND T/H
INPUT
MUX
DD
initiates power-up and acquisition.
+ 0.05V). Bypass REF to GND with a
12-BIT SAR
ADC
V
GND
DD
Pin Description
high to disable DOUT.
MAX1393
MAX1396
LOGIC AND
CONTROL
REGISTER
/CH2 high to select
TIMING
OUTPUT
SHIFT
DD
low to
to GND
UNI/BIP
(CH1/CH2)*
CS
SCLK
OE
DOUT