AD7641BSTZ Analog Devices Inc, AD7641BSTZ Datasheet - Page 20

• Manufacturer Part Number: AD7641BSTZ
• Description: IC ADC 18BIT 2MSPS SAR 48-LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD7641BSTZ

• Data Interface: Serial, Parallel
• Number Of Bits: 18
• Sampling Rate (per Second): 2M
• Number Of Converters: 1
• Power Dissipation (max): 92mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Resolution (bits): 18bit
• Sampling Rate: 2MSPS
• Input Channel Type: Differential
• Supply Current: 23mA
• Digital Ic Case Style: QFP
• No. Of Pins: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7641CBZ - BOARD EVALUATION FOR AD7641
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD7641
POWER SUPPLY
The AD7641 uses three sets of power supply pins: an analog
2.5 V supply AVDD, a digital 2.5 V core supply DVDD, and a
digital input/output interface supply OVDD. The OVDD supply
allows direct interface with any logic working between 2.3 V
and 5.25 V. To reduce the number of supplies needed, the digital
core (DVDD) can be supplied through a simple RC filter from
the analog supply, as shown in
Power Sequencing
The AD7641 is independent of power supply sequencing and
thus free from supply induced voltage latch-up. In addition, it is
very insensitive to power supply variations over a wide
frequency range, as shown in Figure 28.
Power-Up
At power-up, or returning to operational mode from the power-
down mode (PD = high), the AD7641 engages an initialization
process. During this time, the first 128 conversions should be
ignored or the RESET input could be pulsed to engage a faster
initialization process. Refer to the Digital Interface section for
RESET and timing details.
A simple power-on reset circuit, as shown in Figure 23, can be
used to minimize the digital interface. As OVDD powers up, the
capacitor is shorted and brings RESET high; it is then charged
returning RESET to low. However, this circuit only works when
powering up the AD7641 because the power-down mode
(PD = high) does not power down any of the supplies and as a
result, RESET is low.
65.0
62.5
60.0
57.5
55.0
52.5
50.0
47.5
45.0
1
Figure 28. PSRR vs. Frequency
EXT REF
INT REF
10
FREQUENCY (MHz)
Figure 23.
100
1000
10000
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It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital
supply currents even further, drive the digital inputs close to
the power rails (that is, OVDD and OGND).
CONVERSION CONTROL
The AD7641 is controlled by the CNVST input. A falling edge
on CNVST is all that is necessary to initiate a conversion.
Detailed timing diagrams of the conversion process are shown
in
even by the power-down input, PD, until the conversion is
complete. The
RD signals.
CNVST
For optimal performance, the rising edge of
occur after the maximum CNVST low time, t
of conversion.
Although CNVST is a digital signal, it should be designed with
special care with fast, clean edges and levels with minimum
overshoot and undershoot or ringing.
The CNVST trace should be shielded with ground and a low
value serial resistor (for example, 50 Ω) termination should be
added close to the output of the component that drives this line.
In addition, a 50 pF capacitor is recommended to further reduce
the effects of overshoot and undershoot as shown in Figure 23.
For applications where SNR is critical, the CNVST signal should
have very low jitter. This can be achieved by using a dedicated
oscillator for CNVST generation, or by clocking CNVST with a
high frequency, low jitter clock, as shown in Figure 23.
MODE
BUSY
Figure 29. Once initiated, it cannot be restarted or aborted,
ACQUIRE
t
t
3
5
CNVST signal operates independently of CS and
t
Figure 29. Basic Conversion Timing
CONVERT
1
t
7
t
4
t
t
2
6
ACQUIRE
t
8
CNVST
1
, or until the end
should not
CONVERT